{"id":"https://openalex.org/W2054043921","doi":"https://doi.org/10.1109/asicon.2013.6812016","title":"A novel structure of dynamic configurable scan chain bypassing unconcerned segments on the fly","display_name":"A novel structure of dynamic configurable scan chain bypassing unconcerned segments on the fly","publication_year":2013,"publication_date":"2013-10-01","ids":{"openalex":"https://openalex.org/W2054043921","doi":"https://doi.org/10.1109/asicon.2013.6812016","mag":"2054043921"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2013.6812016","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2013.6812016","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 10th International Conference on ASIC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101624040","display_name":"Shengye Wang","orcid":"https://orcid.org/0000-0003-3723-6853"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shengye Wang","raw_affiliation_strings":["State Key Lab of ASIC and System, Fudan University, Shanghai, China","State-Key Lab of ASIC and System, Fudan University, Shanghai 201203, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Lab of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State-Key Lab of ASIC and System, Fudan University, Shanghai 201203, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080190437","display_name":"Wei Cao","orcid":"https://orcid.org/0000-0003-3139-1780"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Wei Cao","raw_affiliation_strings":["State Key Lab of ASIC and System, Fudan University, Shanghai, China","State-Key Lab of ASIC and System, Fudan University, Shanghai 201203, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Lab of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State-Key Lab of ASIC and System, Fudan University, Shanghai 201203, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002732486","display_name":"Lingli Wang","orcid":"https://orcid.org/0000-0002-0579-3527"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lingli Wang","raw_affiliation_strings":["State Key Lab of ASIC and System, Fudan University, Shanghai, China","State-Key Lab of ASIC and System, Fudan University, Shanghai 201203, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Lab of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State-Key Lab of ASIC and System, Fudan University, Shanghai 201203, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5115592118","display_name":"Na Wang","orcid":"https://orcid.org/0000-0002-8314-9972"},"institutions":[{"id":"https://openalex.org/I4210151021","display_name":"Shanghai Institute of Computing Technology","ror":"https://ror.org/05ek0ze18","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210151021"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Na Wang","raw_affiliation_strings":["East China Institute of Computer Technology, Shanghai, China","East China Institute of Computer Technology, Shanghai 200233, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"East China Institute of Computer Technology, Shanghai, China","institution_ids":["https://openalex.org/I4210151021"]},{"raw_affiliation_string":"East China Institute of Computer Technology, Shanghai 200233, China","institution_ids":["https://openalex.org/I4210151021"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5048050916","display_name":"Ping Tao","orcid":null},"institutions":[{"id":"https://openalex.org/I4210151021","display_name":"Shanghai Institute of Computing Technology","ror":"https://ror.org/05ek0ze18","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210151021"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ping Tao","raw_affiliation_strings":["East China Institute of Computer Technology, Shanghai, China","East China Institute of Computer Technology, Shanghai 200233, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"East China Institute of Computer Technology, Shanghai, China","institution_ids":["https://openalex.org/I4210151021"]},{"raw_affiliation_string":"East China Institute of Computer Technology, Shanghai 200233, China","institution_ids":["https://openalex.org/I4210151021"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6343,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.70384085,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7876890301704407},{"id":"https://openalex.org/keywords/chain","display_name":"Chain (unit)","score":0.7138673663139343},{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.6657412648200989},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.6260706186294556},{"id":"https://openalex.org/keywords/on-the-fly","display_name":"On the fly","score":0.5806483626365662},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.5759090185165405},{"id":"https://openalex.org/keywords/boundary","display_name":"Boundary (topology)","score":0.5672929286956787},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5549811720848083},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.44133320450782776},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.41023725271224976},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3848290741443634},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3243497312068939},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10456827282905579},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.09147405624389648},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.08524221181869507},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08311024308204651}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7876890301704407},{"id":"https://openalex.org/C199185054","wikidata":"https://www.wikidata.org/wiki/Q552299","display_name":"Chain (unit)","level":2,"score":0.7138673663139343},{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.6657412648200989},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.6260706186294556},{"id":"https://openalex.org/C2781020372","wikidata":"https://www.wikidata.org/wiki/Q533093","display_name":"On the fly","level":2,"score":0.5806483626365662},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.5759090185165405},{"id":"https://openalex.org/C62354387","wikidata":"https://www.wikidata.org/wiki/Q875399","display_name":"Boundary (topology)","level":2,"score":0.5672929286956787},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5549811720848083},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.44133320450782776},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.41023725271224976},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3848290741443634},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3243497312068939},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10456827282905579},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.09147405624389648},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.08524221181869507},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08311024308204651},{"id":"https://openalex.org/C1276947","wikidata":"https://www.wikidata.org/wiki/Q333","display_name":"Astronomy","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2013.6812016","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2013.6812016","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 10th International Conference on ASIC","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2003313945","https://openalex.org/W2005786026","https://openalex.org/W2105943941","https://openalex.org/W2163124097","https://openalex.org/W2173857044","https://openalex.org/W6675627336"],"related_works":["https://openalex.org/W2620506035","https://openalex.org/W2168810991","https://openalex.org/W2120447654","https://openalex.org/W2977179488","https://openalex.org/W2121199343","https://openalex.org/W201174846","https://openalex.org/W2144453115","https://openalex.org/W4253215698","https://openalex.org/W2169611555","https://openalex.org/W3115158252"],"abstract_inverted_index":{"Most":[0],"of":[1,4,9,34,44,112],"the":[2,17,60,67,92],"implementations":[3],"boundary":[5,46],"scan":[6,47],"chains":[7],"are":[8,27],"fixed":[10],"length,":[11],"typically":[12],"hundreds":[13],"or":[14],"thousands.":[15],"Because":[16],"whole":[18],"chain":[19,48,79],"is":[20,36,49,88,107],"scanned":[21],"every":[22],"time,":[23],"many":[24],"clock":[25],"cycles":[26],"wasted":[28],"when":[29],"only":[30],"a":[31,41,77,102],"small":[32],"part":[33],"it":[35],"concerned.":[37],"In":[38],"this":[39],"paper,":[40],"novel":[42],"structure":[43,97],"configurable":[45],"proposed.":[50],"Its":[51],"length":[52],"and":[53,106],"content":[54],"can":[55,70],"be":[56,71],"reconfigured":[57],"without":[58],"interrupting":[59],"chip's":[61],"functionality.":[62],"Experimental":[63],"result":[64],"shows":[65],"that":[66],"maximum":[68],"frequency":[69],"as":[72,74],"high":[73],"510.4MHz":[75],"for":[76],"full-configurable":[78],"with":[80],"512":[81],"cells,":[82],"under":[83],"32":[84],"nm":[85],"process,":[86],"which":[87],"15.7x":[89],"better":[90],"than":[91],"intuitive":[93],"method.":[94],"The":[95],"proposed":[96],"has":[98],"been":[99],"applied":[100],"to":[101,109],"processor":[103],"prototype":[104],"design,":[105],"expected":[108],"meet":[110],"requirements":[111],"different":[113],"applications.":[114]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
