{"id":"https://openalex.org/W2041999002","doi":"https://doi.org/10.1109/asicon.2013.6811932","title":"The timing control design of 65nm block RAM in FPGA","display_name":"The timing control design of 65nm block RAM in FPGA","publication_year":2013,"publication_date":"2013-10-01","ids":{"openalex":"https://openalex.org/W2041999002","doi":"https://doi.org/10.1109/asicon.2013.6811932","mag":"2041999002"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2013.6811932","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2013.6811932","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 10th International Conference on ASIC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100708912","display_name":"Xinrui Zhang","orcid":"https://orcid.org/0000-0003-1211-821X"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Xinrui Zhang","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100370396","display_name":"Jian Wang","orcid":"https://orcid.org/0000-0002-0579-3041"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jian Wang","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100444003","display_name":"Dan Chen","orcid":"https://orcid.org/0000-0002-7055-141X"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Dan Chen","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081419061","display_name":"Jinmei Lai","orcid":"https://orcid.org/0009-0003-5238-4720"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinmei Lai","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Lichun Bao","orcid":null},"institutions":[{"id":"https://openalex.org/I4210166468","display_name":"Beijing Aerospace Flight Control Center","ror":"https://ror.org/007a14354","country_code":"CN","type":"other","lineage":["https://openalex.org/I4210166468"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lichun Bao","raw_affiliation_strings":["Beijing Aerospace Control Center (BACC)","Beijing Aerospace Control Center (BACC), China"],"affiliations":[{"raw_affiliation_string":"Beijing Aerospace Control Center (BACC)","institution_ids":["https://openalex.org/I4210166468"]},{"raw_affiliation_string":"Beijing Aerospace Control Center (BACC), China","institution_ids":["https://openalex.org/I4210166468"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5006342653","display_name":"Xueling Liu","orcid":"https://orcid.org/0000-0002-0981-2633"},"institutions":[{"id":"https://openalex.org/I4210166468","display_name":"Beijing Aerospace Flight Control Center","ror":"https://ror.org/007a14354","country_code":"CN","type":"other","lineage":["https://openalex.org/I4210166468"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xueling Liu","raw_affiliation_strings":["Beijing Aerospace Control Center (BACC)","Beijing Aerospace Control Center (BACC), China"],"affiliations":[{"raw_affiliation_string":"Beijing Aerospace Control Center (BACC)","institution_ids":["https://openalex.org/I4210166468"]},{"raw_affiliation_string":"Beijing Aerospace Control Center (BACC), China","institution_ids":["https://openalex.org/I4210166468"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5100708912"],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.10919738,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9778000116348267,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9778000116348267,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9685999751091003,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9624000191688538,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6898837089538574},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6713491678237915},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5836930871009827},{"id":"https://openalex.org/keywords/fifo","display_name":"FIFO (computing and electronics)","score":0.5514708757400513},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.5179973244667053},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.48906880617141724},{"id":"https://openalex.org/keywords/fifo-and-lifo-accounting","display_name":"FIFO and LIFO accounting","score":0.4825376868247986},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4687768518924713},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3888775110244751}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6898837089538574},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6713491678237915},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5836930871009827},{"id":"https://openalex.org/C2777145635","wikidata":"https://www.wikidata.org/wiki/Q515636","display_name":"FIFO (computing and electronics)","level":2,"score":0.5514708757400513},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.5179973244667053},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.48906880617141724},{"id":"https://openalex.org/C48721391","wikidata":"https://www.wikidata.org/wiki/Q1265942","display_name":"FIFO and LIFO accounting","level":3,"score":0.4825376868247986},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4687768518924713},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3888775110244751},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2013.6811932","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2013.6811932","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 10th International Conference on ASIC","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1592685492","https://openalex.org/W2124925956","https://openalex.org/W2165733032","https://openalex.org/W6684578899"],"related_works":["https://openalex.org/W2168288612","https://openalex.org/W3145739807","https://openalex.org/W2058492552","https://openalex.org/W2485390638","https://openalex.org/W2626729922","https://openalex.org/W2020531283","https://openalex.org/W2322861814","https://openalex.org/W2945758745","https://openalex.org/W2015441043","https://openalex.org/W2148933941"],"abstract_inverted_index":{"The":[0,13,71],"timing":[1,19,30,59,107],"control":[2,20,31,60,94,108],"design":[3,69,109],"of":[4,32,58,79,87,101,115],"65":[5],"nm-based":[6],"FPGA":[7],"embedded":[8],"Block":[9],"RAM":[10],"is":[11,90,110,119],"presented.":[12],"strategy":[14,54],"involves":[15],"both":[16],"the":[17,27,53,56,67,99,113],"internal":[18],"system":[21],"with":[22,105,112],"test":[23],"reliability":[24,57],"considered":[25],"and":[26,48,83],"status":[28],"flag":[29],"BRAM-based":[33],"FIFO.":[34],"With":[35],"redundant":[36],"circuits":[37],"using":[38],"dynamic":[39],"feedback":[40],"ideology,":[41],"introducing":[42],"an":[43],"optional":[44],"delay":[45,95],"chain":[46],"optimization":[47],"optimizing":[49,64],"clock":[50],"latency":[51],"strategies,":[52],"guarantees":[55],"in":[61,76,93,98,124],"BRAM.":[62],"Meanwhile,":[63],"speed":[65,114],"makes":[66],"proposed":[68,72],"practical.":[70],"BRAM":[73,104],"can":[74],"work":[75,80],"a":[77],"variety":[78],"environments":[81],"correctly":[82],"maximize":[84],"success":[85],"rate":[86],"tapeout.":[88],"It":[89],"41.5%~59.2%":[91],"deceasing":[92],"than":[96,122],"that":[97,123],"structure":[100],"Ref":[102,125],"[7].":[103],"novel":[106],"designed":[111],"400":[116],"MHz,":[117],"which":[118],"25%":[120],"faster":[121],"[9].":[126]},"counts_by_year":[],"updated_date":"2026-04-16T08:26:57.006410","created_date":"2025-10-10T00:00:00"}
