{"id":"https://openalex.org/W2071242375","doi":"https://doi.org/10.1109/asicon.2013.6811915","title":"Weight-based FPGA placement algorithm with wire effect considered","display_name":"Weight-based FPGA placement algorithm with wire effect considered","publication_year":2013,"publication_date":"2013-10-01","ids":{"openalex":"https://openalex.org/W2071242375","doi":"https://doi.org/10.1109/asicon.2013.6811915","mag":"2071242375"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2013.6811915","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2013.6811915","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 10th International Conference on ASIC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5042182109","display_name":"Huagang Li","orcid":"https://orcid.org/0000-0003-3133-2887"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Huagang Li","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002847404","display_name":"Jian Wang","orcid":"https://orcid.org/0000-0003-4361-8946"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jian Wang","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081419061","display_name":"Jinmei Lai","orcid":"https://orcid.org/0009-0003-5238-4720"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinmei Lai","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5042182109"],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.12604274,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.993399977684021,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8915976285934448},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6623256802558899},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5216037034988403},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.4383235573768616},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3894481062889099},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.11888989806175232},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.10358798503875732}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8915976285934448},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6623256802558899},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5216037034988403},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.4383235573768616},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3894481062889099},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.11888989806175232},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.10358798503875732}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2013.6811915","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2013.6811915","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 10th International Conference on ASIC","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4399999976158142,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2024060531","https://openalex.org/W2025849674","https://openalex.org/W2070664546","https://openalex.org/W2075137913","https://openalex.org/W2131979475","https://openalex.org/W2139637699","https://openalex.org/W4253154047","https://openalex.org/W6680692090"],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W2051487156","https://openalex.org/W2073681303","https://openalex.org/W2111241003","https://openalex.org/W2390279801","https://openalex.org/W2096844293","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W2570254841","https://openalex.org/W3183044703"],"abstract_inverted_index":{"Weight-based":[0],"FPGA":[1,15,83],"placement":[2,36,46,101],"algorithm":[3,11,79],"with":[4,17,38,63,88],"wire":[5,39],"effect":[6,40],"considered":[7],"was":[8],"presented.":[9],"The":[10,56],"can":[12],"support":[13,81],"modern":[14,82],"architecture":[16,84],"different":[18,35],"kinds":[19],"of":[20,106],"blocks,":[21],"such":[22],"as":[23],"carry":[24],"chain,":[25],"DSP,":[26],"BRAM,":[27],"etc.":[28],"Different":[29],"weight":[30],"factors":[31],"are":[32],"introduced":[33],"to":[34,53],"blocks":[37],"considered.":[41],"In":[42],"this":[43],"way,":[44],"the":[45,77,95,104],"cost":[47,105],"and":[48],"time":[49],"could":[50,80,98],"be":[51],"optimized":[52],"maximize":[54],"extent.":[55],"experiment":[57],"results,":[58],"targeting":[59],"on":[60,93],"FDP5":[61],"chip":[62],"ten":[64],"million":[65],"system":[66],"gates,":[67],"which":[68],"is":[69],"developed":[70],"by":[71],"Fudan":[72],"University":[73],"independently,":[74],"show":[75],"that":[76],"proposed":[78,96],"perfectly.":[85],"Furthermore,":[86],"compared":[87],"Xilinx's":[89],"CAD":[90],"tool":[91],"ISE,":[92],"average,":[94],"placer":[97],"achieve":[99],"95%":[100],"quality":[102],"at":[103],"a":[107],"3%":[108],"increase":[109],"in":[110],"run":[111],"time.":[112]},"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}