{"id":"https://openalex.org/W2119738294","doi":"https://doi.org/10.1109/asicon.2013.6811840","title":"Design of an optimized low-latency interrupt controller for IMS-DPU","display_name":"Design of an optimized low-latency interrupt controller for IMS-DPU","publication_year":2013,"publication_date":"2013-10-01","ids":{"openalex":"https://openalex.org/W2119738294","doi":"https://doi.org/10.1109/asicon.2013.6811840","mag":"2119738294"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2013.6811840","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2013.6811840","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 10th International Conference on ASIC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109223451","display_name":"Zijia Guo","orcid":null},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zijia Guo","raw_affiliation_strings":["Key Lab of Integrated Microsystems, Shenzhen Graduate School, Shenzhen","The Key Lab of Integrated Microsystems Peking University Shenzhen Graduate School, 518055, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Key Lab of Integrated Microsystems, Shenzhen Graduate School, Shenzhen","institution_ids":[]},{"raw_affiliation_string":"The Key Lab of Integrated Microsystems Peking University Shenzhen Graduate School, 518055, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5115595358","display_name":"Teng Wang","orcid":"https://orcid.org/0000-0002-4975-2831"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Teng Wang","raw_affiliation_strings":["Key Lab of Integrated Microsystems, Shenzhen Graduate School, Shenzhen","The Key Lab of Integrated Microsystems Peking University Shenzhen Graduate School, 518055, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Key Lab of Integrated Microsystems, Shenzhen Graduate School, Shenzhen","institution_ids":[]},{"raw_affiliation_string":"The Key Lab of Integrated Microsystems Peking University Shenzhen Graduate School, 518055, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102009435","display_name":"Xin\u2019an Wang","orcid":"https://orcid.org/0000-0002-9712-8531"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xin-An Wang","raw_affiliation_strings":["Key Lab of Integrated Microsystems, Shenzhen Graduate School, Shenzhen","The Key Lab of Integrated Microsystems Peking University Shenzhen Graduate School, 518055, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Key Lab of Integrated Microsystems, Shenzhen Graduate School, Shenzhen","institution_ids":[]},{"raw_affiliation_string":"The Key Lab of Integrated Microsystems Peking University Shenzhen Graduate School, 518055, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5051059618","display_name":"Ziyi Hu","orcid":"https://orcid.org/0009-0004-8657-4247"},"institutions":[{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"government","lineage":["https://openalex.org/I19820366"]},{"id":"https://openalex.org/I4210090209","display_name":"Institute of Microelectronics","ror":"https://ror.org/009rw8n36","country_code":"SG","type":"facility","lineage":["https://openalex.org/I115228651","https://openalex.org/I4210090209","https://openalex.org/I91275662"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN","SG"],"is_corresponding":false,"raw_author_name":"Ziyi Hu","raw_affiliation_strings":["Institute of Microelectronics of Chinese Academy of Sciences, Beijing","Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029 , China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics of Chinese Academy of Sciences, Beijing","institution_ids":["https://openalex.org/I19820366"]},{"raw_affiliation_string":"Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029 , China","institution_ids":["https://openalex.org/I4210090209","https://openalex.org/I4210119392"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3172,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.63391319,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9955999851226807,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9955999851226807,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9873999953269958,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interrupt","display_name":"Interrupt","score":0.9889326691627502},{"id":"https://openalex.org/keywords/interrupt-handler","display_name":"Interrupt handler","score":0.7422221302986145},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7272023558616638},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6912611126899719},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6195764541625977},{"id":"https://openalex.org/keywords/preemption","display_name":"Preemption","score":0.503961980342865},{"id":"https://openalex.org/keywords/reentrancy","display_name":"Reentrancy","score":0.46573132276535034},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.4422876238822937},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4321925640106201},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36853331327438354},{"id":"https://openalex.org/keywords/microcontroller","display_name":"Microcontroller","score":0.12106761336326599}],"concepts":[{"id":"https://openalex.org/C41661131","wikidata":"https://www.wikidata.org/wiki/Q220764","display_name":"Interrupt","level":3,"score":0.9889326691627502},{"id":"https://openalex.org/C28533478","wikidata":"https://www.wikidata.org/wiki/Q1541162","display_name":"Interrupt handler","level":4,"score":0.7422221302986145},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7272023558616638},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6912611126899719},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6195764541625977},{"id":"https://openalex.org/C206952183","wikidata":"https://www.wikidata.org/wiki/Q1193100","display_name":"Preemption","level":2,"score":0.503961980342865},{"id":"https://openalex.org/C161406801","wikidata":"https://www.wikidata.org/wiki/Q963635","display_name":"Reentrancy","level":2,"score":0.46573132276535034},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.4422876238822937},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4321925640106201},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36853331327438354},{"id":"https://openalex.org/C173018170","wikidata":"https://www.wikidata.org/wiki/Q165678","display_name":"Microcontroller","level":2,"score":0.12106761336326599},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2013.6811840","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2013.6811840","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 10th International Conference on ASIC","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.47999998927116394}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1996777742","https://openalex.org/W2092529530","https://openalex.org/W2097391334","https://openalex.org/W2356102584","https://openalex.org/W4255153885"],"related_works":["https://openalex.org/W2391783641","https://openalex.org/W3022243336","https://openalex.org/W2379223267","https://openalex.org/W1514054908","https://openalex.org/W2097391334","https://openalex.org/W2347462420","https://openalex.org/W2357192602","https://openalex.org/W1984516971","https://openalex.org/W2356538057","https://openalex.org/W3081551578"],"abstract_inverted_index":{"Interrupt":[0],"handling":[1],"mechanism":[2],"is":[3,21,67,142],"an":[4,16],"important":[5],"function":[6],"for":[7,29,111],"multi-core":[8,26,77],"system":[9,27],"to":[10,23,68,120],"work":[11],"collaboratively.":[12],"In":[13,79],"this":[14,105],"paper,":[15],"optimized":[17],"low-latency":[18],"interrupt":[19,37,40,50,54,59,88,93,97],"controller":[20,41,66],"proposed":[22],"support":[24,121],"a":[25,76],"IMS-DPU":[28],"high":[30],"performance":[31,112],"medical":[32],"electronics":[33],"equipment.":[34],"Utilizing":[35],"two":[36],"models,":[38],"the":[39,65,73,118,122,139],"implements":[42],"three":[43],"different":[44],"kinds":[45],"of":[46,64,75,124,156],"interrupts,":[47],"shared":[48],"peripheral":[49,53],"(SPI),":[51],"private":[52],"(PPI)":[55],"and":[56,90,95,99,127,132],"software":[57,125],"generated":[58],"(SGI).":[60],"The":[61,102],"main":[62],"feature":[63],"distribute":[69],"multiple":[70],"interrupts":[71],"across":[72],"cores":[74],"system.":[78],"addition,":[80],"our":[81],"architecture":[82],"supports":[83],"several":[84],"advanced":[85],"features":[86],"like":[87],"pending":[89],"active":[91],"state,":[92],"preemption":[94],"nesting,":[96],"grouping":[98],"security":[100],"extension.":[101],"design":[103],"in":[104,114],"study":[106],"puts":[107],"forward":[108],"special":[109],"optimization":[110],"enhancement":[113],"hardware":[115,128],"structures,":[116],"with":[117,145,149],"aim":[119],"combination":[123],"stack":[126],"stack,":[129],"tail":[130],"chaining":[131],"later":[133],"arrivals.":[134],"FPGA":[135],"prototyping":[136],"results":[137],"justify":[138],"design.":[140],"It":[141],"finally":[143],"implemented":[144],"CSMC":[146],"180nm":[147],"technology":[148],"6.01K":[150],"logic":[151],"gates":[152],"at":[153],"working":[154],"frequency":[155],"200MHz.":[157]},"counts_by_year":[{"year":2016,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
