{"id":"https://openalex.org/W2010750385","doi":"https://doi.org/10.1109/asicon.2011.6157370","title":"A 1.2 V 70 mA low drop-out voltage regulator in 0.13 &amp;#x00B5;m CMOS process","display_name":"A 1.2 V 70 mA low drop-out voltage regulator in 0.13 &amp;#x00B5;m CMOS process","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W2010750385","doi":"https://doi.org/10.1109/asicon.2011.6157370","mag":"2010750385"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2011.6157370","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157370","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5015275660","display_name":"Qin Wu","orcid":"https://orcid.org/0000-0003-4371-4372"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Qin Wu","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100318012","display_name":"Wei Li","orcid":"https://orcid.org/0000-0001-7547-2908"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Wei Li","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100369026","display_name":"Ning Li","orcid":"https://orcid.org/0000-0002-4485-998X"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ning Li","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073819142","display_name":"Junyan Ren","orcid":"https://orcid.org/0009-0009-1356-6314"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Junyan Ren","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5015275660"],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.08878339,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"978","last_page":"981"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/transconductance","display_name":"Transconductance","score":0.7203186750411987},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.6974251866340637},{"id":"https://openalex.org/keywords/line-regulation","display_name":"Line regulation","score":0.6416131854057312},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.6318063735961914},{"id":"https://openalex.org/keywords/bandgap-voltage-reference","display_name":"Bandgap voltage reference","score":0.6007568836212158},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5485986471176147},{"id":"https://openalex.org/keywords/operational-amplifier","display_name":"Operational amplifier","score":0.5414336919784546},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.5026512145996094},{"id":"https://openalex.org/keywords/dropout-voltage","display_name":"Dropout voltage","score":0.5023770332336426},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4753781855106354},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.47068339586257935},{"id":"https://openalex.org/keywords/load-regulation","display_name":"Load regulation","score":0.45308223366737366},{"id":"https://openalex.org/keywords/operational-transconductance-amplifier","display_name":"Operational transconductance amplifier","score":0.4509814977645874},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.4451196491718292},{"id":"https://openalex.org/keywords/voltage-regulator","display_name":"Voltage regulator","score":0.4364716708660126},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.42871007323265076},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.256717711687088}],"concepts":[{"id":"https://openalex.org/C2779283907","wikidata":"https://www.wikidata.org/wiki/Q1632964","display_name":"Transconductance","level":4,"score":0.7203186750411987},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.6974251866340637},{"id":"https://openalex.org/C2777901765","wikidata":"https://www.wikidata.org/wiki/Q6553328","display_name":"Line regulation","level":5,"score":0.6416131854057312},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.6318063735961914},{"id":"https://openalex.org/C127033052","wikidata":"https://www.wikidata.org/wiki/Q48635","display_name":"Bandgap voltage reference","level":5,"score":0.6007568836212158},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5485986471176147},{"id":"https://openalex.org/C145366948","wikidata":"https://www.wikidata.org/wiki/Q178947","display_name":"Operational amplifier","level":4,"score":0.5414336919784546},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.5026512145996094},{"id":"https://openalex.org/C15032970","wikidata":"https://www.wikidata.org/wiki/Q851210","display_name":"Dropout voltage","level":4,"score":0.5023770332336426},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4753781855106354},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.47068339586257935},{"id":"https://openalex.org/C2776098794","wikidata":"https://www.wikidata.org/wiki/Q6663315","display_name":"Load regulation","level":3,"score":0.45308223366737366},{"id":"https://openalex.org/C58117264","wikidata":"https://www.wikidata.org/wiki/Q1239595","display_name":"Operational transconductance amplifier","level":5,"score":0.4509814977645874},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.4451196491718292},{"id":"https://openalex.org/C110706871","wikidata":"https://www.wikidata.org/wiki/Q851210","display_name":"Voltage regulator","level":3,"score":0.4364716708660126},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.42871007323265076},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.256717711687088}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2011.6157370","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157370","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8700000047683716}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W2067658274","https://openalex.org/W2109182259","https://openalex.org/W2117615344","https://openalex.org/W2133201500"],"related_works":["https://openalex.org/W2348464439","https://openalex.org/W2072896344","https://openalex.org/W2225727459","https://openalex.org/W4200415563","https://openalex.org/W2038852706","https://openalex.org/W1966035129","https://openalex.org/W4286304267","https://openalex.org/W3120080380","https://openalex.org/W3081147268","https://openalex.org/W2196780314"],"abstract_inverted_index":{"A":[0,95],"low":[1],"drop-out":[2,25,83],"(LDO)":[3],"voltage":[4,26,72,84],"regulator":[5],"with":[6,81,117],"a":[7,66,82,89,107,118,133],"built-in":[8],"bandgap":[9],"is":[10,40,63,74,122,128,143],"proposed":[11],"in":[12,17],"this":[13],"paper":[14],"and":[15,24,101],"fabricated":[16],"0.13-\u03bcm":[18],"CMOS":[19],"technology.":[20],"The":[21,34,70,124,139],"load":[22,93,96,108,134],"regulation":[23,97],"are":[27],"reduced":[28,41],"by":[29,42,65],"enlarging":[30],"the":[31,37,44,48,55,58,61,150],"pass":[32],"transistor.":[33],"headroom":[35],"of":[36,47,60,85,92,98,103,136],"chip":[38],"area":[39,142],"eliminating":[43],"miller":[45],"capacitor":[46],"two-stage":[49],"Operational":[50],"Transconductance":[51],"Amplifier":[52],"(OTA)":[53],"for":[54,88,106,132],"error":[56],"amplifier,":[57],"loop":[59],"LDO":[62],"compensated":[64],"large":[67],"off-chip":[68],"capacitor.":[69],"input":[71],"range":[73],"from":[75,111],"1.313":[76],"V":[77,80],"to":[78,114],"1.5":[79],"113":[86],"mV":[87,100,105],"70":[90,115,137],"mA":[91,113,116],"current.":[94],"7":[99],"undershoot":[102],"3":[104],"current":[109,127,135],"step":[110],"1":[112],"1-\u03bcs":[119],"rise-up":[120],"time":[121],"measured.":[123],"measured":[125],"quiescent":[126],"about":[129],"93":[130],"\u03bcA":[131],"mA.":[138],"effective":[140],"die":[141],"0.35":[144],"mm":[145],"<sup":[146],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[147],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[148],"including":[149],"testing":[151],"pads.":[152]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}