{"id":"https://openalex.org/W2006903450","doi":"https://doi.org/10.1109/asicon.2011.6157337","title":"Single event upset mitigation for FDP2008","display_name":"Single event upset mitigation for FDP2008","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W2006903450","doi":"https://doi.org/10.1109/asicon.2011.6157337","mag":"2006903450"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2011.6157337","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157337","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005595160","display_name":"Meng Yang","orcid":"https://orcid.org/0000-0003-2862-2015"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Meng Yang","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","State-Key Lab of ASIC and System, Fudan University, Shanghai 201203, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State-Key Lab of ASIC and System, Fudan University, Shanghai 201203, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5006212733","display_name":"Gengsheng Chen","orcid":"https://orcid.org/0000-0003-1879-9415"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Gengsheng Chen","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","State-Key Lab of ASIC and System, Fudan University, Shanghai 201203, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State-Key Lab of ASIC and System, Fudan University, Shanghai 201203, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5005595160"],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.07513128,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"30","issue":null,"first_page":"847","last_page":"849"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.7158150672912598},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7118461728096008},{"id":"https://openalex.org/keywords/single-event-upset","display_name":"Single event upset","score":0.659553587436676},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6462084054946899},{"id":"https://openalex.org/keywords/triple-modular-redundancy","display_name":"Triple modular redundancy","score":0.5716047286987305},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5508865118026733},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5461207628250122},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.517697811126709},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.44551753997802734},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4413376748561859},{"id":"https://openalex.org/keywords/upset","display_name":"Upset","score":0.43783313035964966},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.4244949221611023},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.36722463369369507},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.34627294540405273},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.25820887088775635},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22202864289283752},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.08235108852386475},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07665887475013733}],"concepts":[{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.7158150672912598},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7118461728096008},{"id":"https://openalex.org/C2780073065","wikidata":"https://www.wikidata.org/wiki/Q1476733","display_name":"Single event upset","level":3,"score":0.659553587436676},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6462084054946899},{"id":"https://openalex.org/C196371267","wikidata":"https://www.wikidata.org/wiki/Q3998979","display_name":"Triple modular redundancy","level":3,"score":0.5716047286987305},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5508865118026733},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5461207628250122},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.517697811126709},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.44551753997802734},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4413376748561859},{"id":"https://openalex.org/C2778002589","wikidata":"https://www.wikidata.org/wiki/Q2406791","display_name":"Upset","level":2,"score":0.43783313035964966},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.4244949221611023},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36722463369369507},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.34627294540405273},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.25820887088775635},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22202864289283752},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.08235108852386475},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07665887475013733},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2011.6157337","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157337","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.49000000953674316,"id":"https://metadata.un.org/sdg/13","display_name":"Climate action"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2000571916","https://openalex.org/W2106635847","https://openalex.org/W2116097016","https://openalex.org/W2120034842","https://openalex.org/W2135743241"],"related_works":["https://openalex.org/W2102538861","https://openalex.org/W2765704306","https://openalex.org/W2123934961","https://openalex.org/W1540420234","https://openalex.org/W2161646799","https://openalex.org/W2359969304","https://openalex.org/W764628369","https://openalex.org/W2062230033","https://openalex.org/W2051487197","https://openalex.org/W2271512713"],"abstract_inverted_index":{"Highly":[0],"integrated":[1],"contemporary":[2],"SRAM-based":[3],"Field":[4],"Programmable":[5],"Gate":[6],"Arrays":[7],"(FPGAs)":[8],"lead":[9],"to":[10,44,71],"high":[11],"occurrence-rate":[12],"of":[13,76],"transient":[14],"faults":[15],"induced":[16],"by":[17],"Single":[18],"Event":[19],"Upsets":[20],"(SEUs)":[21],"in":[22],"FPGAs'":[23],"configuration":[24],"memory.":[25],"In":[26],"this":[27],"paper,":[28],"Fudan":[29],"Design":[30],"Environment":[31],"(FDE)":[32],"Triple":[33],"Module":[34],"Redundancy":[35],"(TMR)":[36],"approach":[37],"for":[38],"design":[39,47],"triplication":[40],"has":[41],"been":[42],"devised":[43],"meet":[45],"high-reliability":[46],"on":[48],"FDP2008.":[49],"Throughput":[50],"Logic,":[51],"feedback":[52],"logic,":[53],"I/O":[54],"logic":[55,67],"and":[56,65],"special":[57],"feature":[58],"such":[59],"as":[60],"Shift":[61],"Register":[62],"LUTs":[63],"(SRLs)":[64],"constant":[66],"are":[68],"treated":[69],"differently":[70],"effectively":[72],"mitigate":[73],"the":[74,77],"effects":[75],"SEU":[78],"faults.":[79]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
