{"id":"https://openalex.org/W2043857451","doi":"https://doi.org/10.1109/asicon.2011.6157317","title":"AProgrammable IP Core for LDPC Decoder Based onASIP","display_name":"AProgrammable IP Core for LDPC Decoder Based onASIP","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W2043857451","doi":"https://doi.org/10.1109/asicon.2011.6157317","mag":"2043857451"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2011.6157317","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157317","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Jun Deng","orcid":null},"institutions":[{"id":"https://openalex.org/I4210149211","display_name":"Institute of Semiconductors","ror":"https://ror.org/048dd0611","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210149211"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Jun Deng","raw_affiliation_strings":["Sichuan Institute of Solid-state Circuits, Chongqing, China","Sichuan Institute of Solid-state Circuits, Chongqing, 400060, China"],"affiliations":[{"raw_affiliation_string":"Sichuan Institute of Solid-state Circuits, Chongqing, China","institution_ids":["https://openalex.org/I4210149211"]},{"raw_affiliation_string":"Sichuan Institute of Solid-state Circuits, Chongqing, 400060, China","institution_ids":["https://openalex.org/I4210149211"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100451306","display_name":"Bing Li","orcid":"https://orcid.org/0000-0003-0992-5854"},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Bing Li","raw_affiliation_strings":["School of integrated circuits, South East University, Nanjing, China","School of Integrated Circuits, Southeast University, Nanjing, 210096, China"],"affiliations":[{"raw_affiliation_string":"School of integrated circuits, South East University, Nanjing, China","institution_ids":["https://openalex.org/I76569877"]},{"raw_affiliation_string":"School of Integrated Circuits, Southeast University, Nanjing, 210096, China","institution_ids":["https://openalex.org/I76569877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091475690","display_name":"Lintao Liu","orcid":"https://orcid.org/0000-0002-0071-6741"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Lintao Liu","raw_affiliation_strings":["Science and Technology on Analog Integrated Circuit Laboratory, Chongqing, China","Science and Technology on Analog Integrated Circuit Laboratory, Chongqing, 400060, China"],"affiliations":[{"raw_affiliation_string":"Science and Technology on Analog Integrated Circuit Laboratory, Chongqing, China","institution_ids":[]},{"raw_affiliation_string":"Science and Technology on Analog Integrated Circuit Laboratory, Chongqing, 400060, China","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5115593693","display_name":"Rui Chen","orcid":"https://orcid.org/0000-0001-9379-2753"},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Rui Chen","raw_affiliation_strings":["School of integrated circuits, South East University, Nanjing, China","School of Integrated Circuits, Southeast University, Nanjing, 210096, China"],"affiliations":[{"raw_affiliation_string":"School of integrated circuits, South East University, Nanjing, China","institution_ids":["https://openalex.org/I76569877"]},{"raw_affiliation_string":"School of Integrated Circuits, Southeast University, Nanjing, 210096, China","institution_ids":["https://openalex.org/I76569877"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210149211"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.14066757,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"764","last_page":"767"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10125","display_name":"Advanced Wireless Communication Techniques","score":0.9937000274658203,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12029","display_name":"DNA and Biological Computing","score":0.9861000180244446,"subfield":{"id":"https://openalex.org/subfields/1312","display_name":"Molecular Biology"},"field":{"id":"https://openalex.org/fields/13","display_name":"Biochemistry, Genetics and Molecular Biology"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7437893152236938},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6895092129707336},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.6703153848648071},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.5292966365814209},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4988870620727539},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4731506109237671},{"id":"https://openalex.org/keywords/low-density-parity-check-code","display_name":"Low-density parity-check code","score":0.4686763882637024},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.45098528265953064},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.42185068130493164},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.41990092396736145},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4173886179924011},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.360762357711792},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3599820137023926},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3572665750980377},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.12359756231307983},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10760530829429626},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.10014143586158752},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09232980012893677}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7437893152236938},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6895092129707336},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.6703153848648071},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.5292966365814209},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4988870620727539},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4731506109237671},{"id":"https://openalex.org/C67692717","wikidata":"https://www.wikidata.org/wiki/Q187444","display_name":"Low-density parity-check code","level":3,"score":0.4686763882637024},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.45098528265953064},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.42185068130493164},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.41990092396736145},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4173886179924011},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.360762357711792},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3599820137023926},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3572665750980377},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.12359756231307983},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10760530829429626},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.10014143586158752},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09232980012893677}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2011.6157317","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157317","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8799999952316284,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W619359362","https://openalex.org/W2118559083","https://openalex.org/W2128765501","https://openalex.org/W2137813581","https://openalex.org/W2144962541","https://openalex.org/W4256648168"],"related_works":["https://openalex.org/W1512285683","https://openalex.org/W2151236218","https://openalex.org/W4234601000","https://openalex.org/W2139569078","https://openalex.org/W2197466303","https://openalex.org/W2187918628","https://openalex.org/W2135636985","https://openalex.org/W1607849496","https://openalex.org/W2147419146","https://openalex.org/W2254425074"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"a":[3,9,49,76,85,101,108],"programmable":[4,50],"soft":[5],"IP":[6,71],"core":[7],"of":[8,105,111],"LDPC":[10],"decoder":[11,38,61],"based":[12,33,80],"on":[13,34,81,84,94],"ASIP":[14,35],"(application-specific":[15],"instruction":[16],"set":[17],"processor)":[18],"which":[19],"can":[20,39],"support":[21],"multi-mode":[22],"specified":[23],"in":[24,48],"the":[25,29,37,42,45,56,60,68,70,91,118],"IEEE802.11n":[26,46],"standard.":[27],"With":[28],"presented":[30],"specific":[31],"microinstructions":[32],"architecture,":[36],"process":[40],"all":[41],"codes":[43],"for":[44],"standard":[47],"approach,":[51],"effectively,":[52],"and":[53,107,117],"due":[54],"to":[55],"proposed":[57],"6-stage":[58],"pipeline,":[59],"performance":[62],"is":[63,122],"improved":[64],"greatly.":[65],"To":[66],"verify":[67],"design,":[69],"has":[72],"been":[73],"integrated":[74],"into":[75],"embedded":[77],"processor":[78],"system":[79],"Xilinx":[82,86],"EDK":[83],"Virtex5":[87],"FPGA":[88],"component.":[89],"Finally,":[90],"Logic":[92],"synthesis":[93],"0.18\u03bcm":[95],"CMOS":[96],"technology":[97],"from":[98],"UMC":[99],"reveals":[100],"maximum":[102],"clock":[103],"frequency":[104],"203MHz":[106],"total":[109],"area":[110],"3.94mm":[112],"<sup":[113],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[114],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[115],",":[116],"corresponding":[119],"power":[120],"consumption":[121],"below":[123],"326.49mW.":[124]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-04-16T08:26:57.006410","created_date":"2025-10-10T00:00:00"}
