{"id":"https://openalex.org/W2140371912","doi":"https://doi.org/10.1109/asicon.2011.6157316","title":"A hardware accelerator for speech recognition applications","display_name":"A hardware accelerator for speech recognition applications","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W2140371912","doi":"https://doi.org/10.1109/asicon.2011.6157316","mag":"2140371912"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2011.6157316","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157316","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006867079","display_name":"Tao Chen","orcid":"https://orcid.org/0009-0002-4305-5960"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Tao Chen","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","State Key Lab of ASIC and System, Fudan University Shanghai 200433, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Lab of ASIC and System, Fudan University Shanghai 200433, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002095628","display_name":"Jiawei Zheng","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jiawei Zheng","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","State Key Lab of ASIC and System, Fudan University Shanghai 200433, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Lab of ASIC and System, Fudan University Shanghai 200433, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054858405","display_name":"X. X. Zhang","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xingsi Zhang","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","State Key Lab of ASIC and System, Fudan University Shanghai 200433, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Lab of ASIC and System, Fudan University Shanghai 200433, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034983873","display_name":"Shengchang Cai","orcid":"https://orcid.org/0000-0003-0936-1593"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shengchang Cai","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","State Key Lab of ASIC and System, Fudan University Shanghai 200433, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Lab of ASIC and System, Fudan University Shanghai 200433, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046894730","display_name":"Yun Chen","orcid":"https://orcid.org/0000-0002-5770-8224"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yun Chen","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","State Key Lab of ASIC and System, Fudan University Shanghai 200433, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Lab of ASIC and System, Fudan University Shanghai 200433, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5006867079"],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.16283287,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"760","last_page":"763"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9922999739646912,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7957396507263184},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7847877740859985},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.7628337144851685},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"Hardware acceleration","score":0.6302076578140259},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5848814249038696},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.5839539766311646},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5833181142807007},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.469556599855423},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.41672176122665405},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.18537119030952454}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7957396507263184},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7847877740859985},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.7628337144851685},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.6302076578140259},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5848814249038696},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.5839539766311646},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5833181142807007},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.469556599855423},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.41672176122665405},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.18537119030952454}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2011.6157316","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157316","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.41999998688697815,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2059706055","https://openalex.org/W2108924585","https://openalex.org/W2144802783","https://openalex.org/W2156885227","https://openalex.org/W2165356296","https://openalex.org/W2473996932","https://openalex.org/W6681422399","https://openalex.org/W6720437123"],"related_works":["https://openalex.org/W2544043553","https://openalex.org/W2546284597","https://openalex.org/W2348562861","https://openalex.org/W2387264083","https://openalex.org/W2540393334","https://openalex.org/W2604877941","https://openalex.org/W1983570530","https://openalex.org/W2390042878","https://openalex.org/W2062932566","https://openalex.org/W2390885485"],"abstract_inverted_index":{"A":[0],"hardware/software":[1],"co-processing":[2],"system":[3,14,30,47,85],"for":[4],"speech":[5,45],"recognition":[6,46,54,64],"applications":[7],"is":[8,31,68],"proposed":[9,84],"in":[10,36,70],"this":[11],"paper.":[12],"The":[13,66],"consists":[15],"of":[16,43],"a":[17,21,76,91],"soft-core":[18],"microprocessor":[19],"and":[20,56,73],"dedicated":[22],"hardware":[23,50],"accelerator":[24],"implemented":[25],"on":[26,75],"an":[27],"FPGA.":[28,79],"This":[29],"intended":[32],"to":[33,48],"be":[34],"used":[35],"embedded":[37],"devices.":[38],"By":[39],"offloading":[40],"computation-intensive":[41],"parts":[42],"the":[44,49,83],"accelerator,":[51],"both":[52],"faster":[53,89],"speed":[55],"lower":[57],"power":[58],"consumption":[59],"are":[60],"achieved":[61],"without":[62],"degrading":[63],"accuracy.":[65],"design":[67],"described":[69],"Verilog":[71],"HDL":[72],"synthesized":[74],"Xilinx":[77],"Virtex-5":[78],"Tests":[80],"show":[81],"that":[82],"runs":[86],"2.18":[87],"times":[88],"than":[90],"pure":[92],"software":[93],"system.":[94]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
