{"id":"https://openalex.org/W2043733028","doi":"https://doi.org/10.1109/asicon.2011.6157231","title":"A 14-bit 2-GS/s DAC with SFDR&amp;#x003E;70dB up to 1-GHz in 65-nm CMOS","display_name":"A 14-bit 2-GS/s DAC with SFDR&amp;#x003E;70dB up to 1-GHz in 65-nm CMOS","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W2043733028","doi":"https://doi.org/10.1109/asicon.2011.6157231","mag":"2043733028"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2011.6157231","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157231","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103018556","display_name":"Ran Li","orcid":"https://orcid.org/0009-0002-4612-6920"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Ran Li","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","[State Key Laboratory of ASIC & System Fudan University, Shanghai, China]"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"[State Key Laboratory of ASIC & System Fudan University, Shanghai, China]","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101722128","display_name":"Zhao Qi","orcid":"https://orcid.org/0000-0002-4987-3051"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qi Zhao","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","[State Key Laboratory of ASIC & System Fudan University, Shanghai, China]"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"[State Key Laboratory of ASIC & System Fudan University, Shanghai, China]","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042914294","display_name":"Ting Yi","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ting Yi","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","[State Key Laboratory of ASIC & System Fudan University, Shanghai, China]"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"[State Key Laboratory of ASIC & System Fudan University, Shanghai, China]","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111788483","display_name":"Zhiliang Hong","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhiliang Hong","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","[State Key Laboratory of ASIC & System Fudan University, Shanghai, China]"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"[State Key Laboratory of ASIC & System Fudan University, Shanghai, China]","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5103018556"],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.2098,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.57086699,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"500","last_page":"503"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/spurious-free-dynamic-range","display_name":"Spurious-free dynamic range","score":0.9456679821014404},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7634354829788208},{"id":"https://openalex.org/keywords/bit","display_name":"Bit (key)","score":0.6840094923973083},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.5304098725318909},{"id":"https://openalex.org/keywords/12-bit","display_name":"12-bit","score":0.45905980467796326},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.41806501150131226},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3805010914802551},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.34577804803848267},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.3385583758354187},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19922950863838196},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.06009387969970703}],"concepts":[{"id":"https://openalex.org/C119293636","wikidata":"https://www.wikidata.org/wiki/Q657480","display_name":"Spurious-free dynamic range","level":3,"score":0.9456679821014404},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7634354829788208},{"id":"https://openalex.org/C117011727","wikidata":"https://www.wikidata.org/wiki/Q1278488","display_name":"Bit (key)","level":2,"score":0.6840094923973083},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.5304098725318909},{"id":"https://openalex.org/C2776310492","wikidata":"https://www.wikidata.org/wiki/Q3271420","display_name":"12-bit","level":3,"score":0.45905980467796326},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.41806501150131226},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3805010914802551},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.34577804803848267},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.3385583758354187},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19922950863838196},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.06009387969970703}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2011.6157231","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157231","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.800000011920929,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1536273088","https://openalex.org/W2035705158","https://openalex.org/W2083850521","https://openalex.org/W2097839301","https://openalex.org/W2098418255","https://openalex.org/W2107876553","https://openalex.org/W2129057069","https://openalex.org/W2131805104","https://openalex.org/W2144306575","https://openalex.org/W2170121471","https://openalex.org/W6659241337","https://openalex.org/W6681294276"],"related_works":["https://openalex.org/W1911569504","https://openalex.org/W2076001147","https://openalex.org/W2619813440","https://openalex.org/W1737812324","https://openalex.org/W2997838140","https://openalex.org/W2811080238","https://openalex.org/W2101363100","https://openalex.org/W2760143382","https://openalex.org/W4387831768","https://openalex.org/W2058202271"],"abstract_inverted_index":{"A":[0],"14-bit":[1],"2-GS/s":[2,63],"5-5-4":[3],"segmented":[4],"current-steering":[5],"digital-to-analog":[6],"converter":[7],"is":[8,30,38,89],"presented":[9],"in":[10,91],"this":[11,52],"paper.":[12],"To":[13],"improve":[14],"the":[15,28],"high":[16],"frequency":[17,59],"performance,":[18],"a":[19,66,73],"\u201cfast":[20],"switching\u201d":[21],"technique":[22],"which":[23],"adds":[24],"additional":[25],"biasing":[26],"to":[27,62],"current-switch":[29],"adopted.":[31],"Also":[32],"data":[33],"dependent":[34],"clock":[35],"loading":[36],"effect":[37],"minimized":[39],"with":[40,77],"better":[41],"switch":[42],"control":[43],"and":[44,64,95],"double":[45],"latch":[46],"method.":[47],"Post-layout":[48],"simulation":[49],"shows":[50],"that":[51],"DAC":[53],"maintains":[54],"70-dB":[55],"SFDR":[56],"over":[57],"Nyquist":[58],"band":[60],"up":[61],"dissipates":[65],"power":[67],"of":[68,81,100],"82":[69],"mW":[70],"while":[71],"driving":[72],"50":[74],"\u03a9":[75],"load":[76],"an":[78,97],"output":[79],"swing":[80],"2.5V":[82],"<sub":[83],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[84,104],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">pp</sub>":[85],".":[86,106],"The":[87],"chip":[88],"designed":[90],"65nm":[92],"CMOS":[93],"technology":[94],"has":[96],"active":[98],"area":[99],"0.9":[101],"mm":[102],"<sup":[103],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[105]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
