{"id":"https://openalex.org/W2074770808","doi":"https://doi.org/10.1109/asicon.2011.6157202","title":"Automatic layout generator for embedded FPGA cores","display_name":"Automatic layout generator for embedded FPGA cores","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W2074770808","doi":"https://doi.org/10.1109/asicon.2011.6157202","mag":"2074770808"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2011.6157202","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157202","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5001715939","display_name":"Chaofan Yu","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Chaofan Yu","raw_affiliation_strings":["State-Key-Laboratory of ASIC and System, Fudan University, Shanghai, China","State-Key Lab of ASIC and System, Fudan University, Shanghai 201203, China"],"affiliations":[{"raw_affiliation_string":"State-Key-Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State-Key Lab of ASIC and System, Fudan University, Shanghai 201203, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002732486","display_name":"Lingli Wang","orcid":"https://orcid.org/0000-0002-0579-3527"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lingli Wang","raw_affiliation_strings":["State-Key-Laboratory of ASIC and System, Fudan University, Shanghai, China","State-Key Lab of ASIC and System, Fudan University, Shanghai 201203, China"],"affiliations":[{"raw_affiliation_string":"State-Key-Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State-Key Lab of ASIC and System, Fudan University, Shanghai 201203, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103281733","display_name":"Xuegong Zhou","orcid":"https://orcid.org/0000-0003-4178-4094"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xuegong Zhou","raw_affiliation_strings":["State-Key-Lab of ASIC and System, Fudan University, Shanghai, China","State-Key Lab of ASIC and System, Fudan University, Shanghai 201203, China"],"affiliations":[{"raw_affiliation_string":"State-Key-Lab of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State-Key Lab of ASIC and System, Fudan University, Shanghai 201203, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5001715939"],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.12159969,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"385","last_page":"388"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.9154610633850098},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6936233639717102},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.6494724750518799},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6350473761558533},{"id":"https://openalex.org/keywords/generator","display_name":"Generator (circuit theory)","score":0.6267347931861877},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6209421753883362},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.5184778571128845},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.46040570735931396},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4579041004180908},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.45419955253601074},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.4122995138168335},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34294962882995605},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.08776339888572693},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.06185096502304077},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.055256038904190063}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.9154610633850098},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6936233639717102},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.6494724750518799},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6350473761558533},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.6267347931861877},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6209421753883362},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.5184778571128845},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.46040570735931396},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4579041004180908},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.45419955253601074},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.4122995138168335},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34294962882995605},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.08776339888572693},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.06185096502304077},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.055256038904190063},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2011.6157202","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157202","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.4699999988079071,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2096344591","https://openalex.org/W2121903852","https://openalex.org/W2151335319","https://openalex.org/W2162628682","https://openalex.org/W4235244711"],"related_works":["https://openalex.org/W2998132311","https://openalex.org/W2207067480","https://openalex.org/W4383823603","https://openalex.org/W1692883217","https://openalex.org/W2406926880","https://openalex.org/W2332075903","https://openalex.org/W1579891439","https://openalex.org/W4378695296","https://openalex.org/W2416897075","https://openalex.org/W3154171573"],"abstract_inverted_index":{"There":[0],"is":[1,56,71,92],"a":[2,23,52],"growing":[3],"tendency":[4],"for":[5],"FPGA":[6,27,48,54,68,90],"(Field":[7],"Programmable":[8],"Gate":[9],"Array)":[10],"IP":[11],"(Intellectual":[12],"Property)":[13],"cores":[14,28],"to":[15,65],"be":[16],"embedded":[17,26],"in":[18,41],"an":[19,61],"SOC":[20,35,39],"(System":[21],"On":[22],"Chip).":[24],"The":[25],"can":[29],"improve":[30],"the":[31,34,42,45,76,84,96],"flexibility":[32],"of":[33,47],"chip.":[36],"However,":[37],"different":[38],"varies":[40],"demands":[43],"on":[44,89],"scale":[46],"tile":[49],"array.":[50],"Therefore,":[51],"scalable":[53],"generator":[55,64,87],"required.":[57],"In":[58],"this":[59],"paper,":[60],"automatic":[62],"layout":[63,86],"support":[66],"user-defined":[67],"array":[69],"size":[70],"introduced":[72],"and":[73],"compared":[74],"with":[75],"previous":[77,97],"related":[78],"works.":[79],"This":[80],"paper":[81],"shows":[82],"that":[83],"proposed":[85],"based":[88],"tiles":[91],"more":[93],"practical":[94],"than":[95],"tools.":[98]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}