{"id":"https://openalex.org/W1982238933","doi":"https://doi.org/10.1109/asicon.2011.6157188","title":"RRA-based multi-objective optimization to mitigate the worst cases of placement","display_name":"RRA-based multi-objective optimization to mitigate the worst cases of placement","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W1982238933","doi":"https://doi.org/10.1109/asicon.2011.6157188","mag":"1982238933"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2011.6157188","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157188","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5076001747","display_name":"Yiqiang Sheng","orcid":null},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yiqiang Sheng","raw_affiliation_strings":["Department of Communication and Integrated Systems, Tokyo Institute of Technology, Tokyo, Japan","Department of Communication and Integrated Systems, Tokyo Institute of Technology, 152-8852, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Communication and Integrated Systems, Tokyo Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]},{"raw_affiliation_string":"Department of Communication and Integrated Systems, Tokyo Institute of Technology, 152-8852, Japan","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100710412","display_name":"Atsushi Takahashi","orcid":"https://orcid.org/0000-0003-3821-5325"},"institutions":[{"id":"https://openalex.org/I98285908","display_name":"The University of Osaka","ror":"https://ror.org/035t8zc32","country_code":"JP","type":"education","lineage":["https://openalex.org/I98285908"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Atsushi Takahashi","raw_affiliation_strings":["Division of Electrical, Electronic and Information Engineering, Osaka University, Suita-shi, Japan","Division of Electrical, Electronic and Information Engineering, Osaka University, Suita-shi, 565-0871, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Division of Electrical, Electronic and Information Engineering, Osaka University, Suita-shi, Japan","institution_ids":["https://openalex.org/I98285908"]},{"raw_affiliation_string":"Division of Electrical, Electronic and Information Engineering, Osaka University, Suita-shi, 565-0871, Japan","institution_ids":["https://openalex.org/I98285908"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5089756558","display_name":"Shuichi Ueno","orcid":"https://orcid.org/0000-0002-2611-962X"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Shuichi Ueno","raw_affiliation_strings":["Department of Communication and Integrated Systems, Tokyo Institute of Technology, Tokyo, Japan","Department of Communication and Integrated Systems, Tokyo Institute of Technology, 152-8852, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Communication and Integrated Systems, Tokyo Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]},{"raw_affiliation_string":"Department of Communication and Integrated Systems, Tokyo Institute of Technology, 152-8852, Japan","institution_ids":["https://openalex.org/I114531698"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.4475,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.52776883,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"153","issue":null,"first_page":"329","last_page":"332"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.8164017796516418},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7158495783805847},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.6371035575866699},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.5822407603263855},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5593962669372559},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5211246609687805},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5184223651885986},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.49842190742492676},{"id":"https://openalex.org/keywords/relay","display_name":"Relay","score":0.44719624519348145},{"id":"https://openalex.org/keywords/genetic-algorithm","display_name":"Genetic algorithm","score":0.4190623164176941},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4012311100959778},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3819437623023987},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.2928121089935303},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2253718078136444},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08207720518112183}],"concepts":[{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.8164017796516418},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7158495783805847},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.6371035575866699},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.5822407603263855},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5593962669372559},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5211246609687805},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5184223651885986},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.49842190742492676},{"id":"https://openalex.org/C2778156585","wikidata":"https://www.wikidata.org/wiki/Q174053","display_name":"Relay","level":3,"score":0.44719624519348145},{"id":"https://openalex.org/C8880873","wikidata":"https://www.wikidata.org/wiki/Q187787","display_name":"Genetic algorithm","level":2,"score":0.4190623164176941},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4012311100959778},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3819437623023987},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.2928121089935303},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2253718078136444},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08207720518112183},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2011.6157188","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157188","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.5699999928474426,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320325836","display_name":"Tokyo University of Agriculture and Technology","ror":"https://ror.org/00qg0kr10"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1988975692","https://openalex.org/W2057860090","https://openalex.org/W2100740271","https://openalex.org/W2106366463","https://openalex.org/W2118912214","https://openalex.org/W2121582360","https://openalex.org/W2127012874","https://openalex.org/W2131979475","https://openalex.org/W2140704214","https://openalex.org/W2148777220","https://openalex.org/W2152434407","https://openalex.org/W2154462472","https://openalex.org/W2156347261","https://openalex.org/W2157291428","https://openalex.org/W2158458634","https://openalex.org/W4230562647","https://openalex.org/W4231579915","https://openalex.org/W4239364405","https://openalex.org/W4239854918","https://openalex.org/W4247393779","https://openalex.org/W6682339546","https://openalex.org/W6683303788","https://openalex.org/W6812656389"],"related_works":["https://openalex.org/W2058965144","https://openalex.org/W2164382479","https://openalex.org/W2146343568","https://openalex.org/W98480971","https://openalex.org/W2150291671","https://openalex.org/W2013643406","https://openalex.org/W2027972911","https://openalex.org/W2081032080","https://openalex.org/W2134733504","https://openalex.org/W2144460576"],"abstract_inverted_index":{"As":[0],"VLSI/PCB":[1],"design":[2,21],"keeps":[3],"going":[4],"through":[5],"higher":[6],"complexity,":[7],"it":[8],"is":[9],"increasingly":[10],"important":[11],"to":[12,24,71,110],"mitigate":[13],"the":[14,37,73,84],"worst":[15],"cases":[16],"of":[17,51,75,105,125],"placement":[18,42,78],"in":[19,22],"physical":[20],"order":[23],"get":[25],"an":[26],"acceptable":[27],"solution":[28],"within":[29],"shorter":[30],"runtime.":[31],"This":[32],"paper":[33],"mainly":[34],"focuses":[35],"on":[36,83,100],"worst-case":[38,94,115],"mitigation":[39],"for":[40,77,96,117],"multi-objective":[41],"by":[43,55],"using":[44],"relay-race":[45],"algorithm":[46,63],"(RRA).":[47],"Several":[48],"intuitive":[49],"advantages":[50],"RRA":[52,76,90,113],"are":[53,69],"discussed":[54],"comparing":[56,87],"with":[57,79,88,121],"simulated":[58],"annealing":[59],"(SA)":[60],"and":[61,66],"genetic":[62],"(GA).":[64],"MCNC":[65],"ami49_X":[67],"benchmarks":[68,120],"used":[70],"test":[72],"effectiveness":[74],"multiple":[80],"objectives.":[81],"Based":[82],"experimental":[85],"data":[86],"SA,":[89],"obtains":[91],"near":[92,122],"24%":[93],"improvement":[95,116],"interconnect":[97],"power":[98],"consumption":[99],"average":[101],"without":[102],"any":[103],"degradation":[104],"maximal":[106],"delay.":[107],"With":[108],"respect":[109],"area":[111],"minimization,":[112],"gets":[114],"all":[118],"tested":[119],"50%":[123],"runtime":[124],"SA":[126],"(2X":[127],"speedup).":[128]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}