{"id":"https://openalex.org/W2057429705","doi":"https://doi.org/10.1109/asicon.2011.6157187","title":"VLSI interconnect delay analysis method for ramp input signal","display_name":"VLSI interconnect delay analysis method for ramp input signal","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W2057429705","doi":"https://doi.org/10.1109/asicon.2011.6157187","mag":"2057429705"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2011.6157187","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157187","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074386200","display_name":"Nobuyuki Mihara","orcid":null},"institutions":[{"id":"https://openalex.org/I17056963","display_name":"The University of Kitakyushu","ror":"https://ror.org/03mfefw72","country_code":"JP","type":"education","lineage":["https://openalex.org/I17056963"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Nobuyuki Mihara","raw_affiliation_strings":["University of Kitakyushu, JAPAN","University of Kitakyushu, Japan#TAB#"],"affiliations":[{"raw_affiliation_string":"University of Kitakyushu, JAPAN","institution_ids":["https://openalex.org/I17056963"]},{"raw_affiliation_string":"University of Kitakyushu, Japan#TAB#","institution_ids":["https://openalex.org/I17056963"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110223905","display_name":"Goro Suzuki","orcid":null},"institutions":[{"id":"https://openalex.org/I17056963","display_name":"The University of Kitakyushu","ror":"https://ror.org/03mfefw72","country_code":"JP","type":"education","lineage":["https://openalex.org/I17056963"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Goro Suzuki","raw_affiliation_strings":["University of Kitakyushu, JAPAN","University of Kitakyushu, Japan#TAB#"],"affiliations":[{"raw_affiliation_string":"University of Kitakyushu, JAPAN","institution_ids":["https://openalex.org/I17056963"]},{"raw_affiliation_string":"University of Kitakyushu, Japan#TAB#","institution_ids":["https://openalex.org/I17056963"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5074386200"],"corresponding_institution_ids":["https://openalex.org/I17056963"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.10946896,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"j91","issue":null,"first_page":"324","last_page":"328"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.8650161027908325},{"id":"https://openalex.org/keywords/weibull-distribution","display_name":"Weibull distribution","score":0.703406035900116},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6260634660720825},{"id":"https://openalex.org/keywords/transfer-function","display_name":"Transfer function","score":0.5807076096534729},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5738234519958496},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5562804937362671},{"id":"https://openalex.org/keywords/base","display_name":"Base (topology)","score":0.49326246976852417},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.4772917330265045},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.4432622194290161},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21211358904838562},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.19884300231933594},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12771505117416382},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10521122813224792}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.8650161027908325},{"id":"https://openalex.org/C173291955","wikidata":"https://www.wikidata.org/wiki/Q732332","display_name":"Weibull distribution","level":2,"score":0.703406035900116},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6260634660720825},{"id":"https://openalex.org/C81299745","wikidata":"https://www.wikidata.org/wiki/Q334269","display_name":"Transfer function","level":2,"score":0.5807076096534729},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5738234519958496},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5562804937362671},{"id":"https://openalex.org/C42058472","wikidata":"https://www.wikidata.org/wiki/Q810214","display_name":"Base (topology)","level":2,"score":0.49326246976852417},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.4772917330265045},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.4432622194290161},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21211358904838562},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.19884300231933594},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12771505117416382},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10521122813224792},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C147789679","wikidata":"https://www.wikidata.org/wiki/Q11372","display_name":"Physical chemistry","level":1,"score":0.0},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2011.6157187","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157187","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4699999988079071,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W571322228","https://openalex.org/W1984588379","https://openalex.org/W2007380193","https://openalex.org/W2018785091","https://openalex.org/W2123618761","https://openalex.org/W2154363431","https://openalex.org/W2155302120","https://openalex.org/W2169269717","https://openalex.org/W3021269648","https://openalex.org/W4238749172","https://openalex.org/W4247970051","https://openalex.org/W6685068509","https://openalex.org/W6829636747"],"related_works":["https://openalex.org/W3083898685","https://openalex.org/W1973754976","https://openalex.org/W189075692","https://openalex.org/W2081032080","https://openalex.org/W2134733504","https://openalex.org/W4242813950","https://openalex.org/W1991973217","https://openalex.org/W2144460576","https://openalex.org/W2084737927","https://openalex.org/W2157788653"],"abstract_inverted_index":{"Many":[0],"methods":[1],"for":[2],"VLSI":[3,76],"interconnect":[4],"delay":[5],"analysis":[6],"based":[7],"on":[8],"the":[9],"transfer":[10,25],"function":[11,26],"have":[12],"been":[13],"developed":[14],"instead":[15],"of":[16],"differential":[17],"equation":[18],"base":[19,27,54],"circuit":[20],"analysis.":[21],"This":[22,57],"paper":[23],"proposes":[24],"method":[28,59],"named":[29],"DPW.":[30],"DPW":[31],"employs":[32],"conventional":[33,66],"Weibull":[34,67],"distribution":[35,68],"method,":[36],"but":[37],"we":[38],"modified":[39],"it":[40],"to":[41],"cope":[42],"with":[43,65],"ramp":[44],"form":[45],"driver":[46],"output":[47],"signal":[48],"calculated":[49],"by":[50],"popular":[51],"effective":[52],"capacitance":[53],"gate":[55],"modeler.":[56],"proposal":[58],"yields":[60],"very":[61],"high":[62],"accuracy":[63],"compared":[64],"method.":[69],"Experimental":[70],"results":[71],"are":[72],"presented":[73],"using":[74],"industrial":[75],"design":[77],"data.":[78]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}