{"id":"https://openalex.org/W1986044127","doi":"https://doi.org/10.1109/asicon.2011.6157184","title":"Design of a single-ended cell based 65nm 32&amp;amp;#x00D7;32b 4R2W register file","display_name":"Design of a single-ended cell based 65nm 32&amp;amp;#x00D7;32b 4R2W register file","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W1986044127","doi":"https://doi.org/10.1109/asicon.2011.6157184","mag":"1986044127"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2011.6157184","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157184","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110312724","display_name":"Baoyu Xiong","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Baoyu Xiong","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100343567","display_name":"Xingxing Zhang","orcid":"https://orcid.org/0000-0002-9838-6962"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xingxing Zhang","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100820799","display_name":"Jun Han","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jun Han","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017560036","display_name":"Zhiyi Yu","orcid":"https://orcid.org/0000-0002-8802-0457"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhiyi Yu","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100656792","display_name":"Xiaoyang Zeng","orcid":"https://orcid.org/0000-0003-3986-137X"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaoyang Zeng","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.4475,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.5297178,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"311","last_page":"314"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.9065036177635193},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7548860311508179},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4892079830169678},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4687177240848541},{"id":"https://openalex.org/keywords/porting","display_name":"Porting","score":0.4531233608722687},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4473443031311035},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.28843677043914795},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.19858607649803162},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1657363772392273},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12630179524421692},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09559190273284912}],"concepts":[{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.9065036177635193},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7548860311508179},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4892079830169678},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4687177240848541},{"id":"https://openalex.org/C106251023","wikidata":"https://www.wikidata.org/wiki/Q851989","display_name":"Porting","level":3,"score":0.4531233608722687},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4473443031311035},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.28843677043914795},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.19858607649803162},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1657363772392273},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12630179524421692},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09559190273284912},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2011.6157184","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157184","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.75}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1498071943","https://openalex.org/W1981720104","https://openalex.org/W2046130163","https://openalex.org/W2109047165","https://openalex.org/W2128876494","https://openalex.org/W6662178971"],"related_works":["https://openalex.org/W2356602486","https://openalex.org/W2351992668","https://openalex.org/W2324828474","https://openalex.org/W2374315191","https://openalex.org/W2391207559","https://openalex.org/W2384715785","https://openalex.org/W2349624418","https://openalex.org/W2064459023","https://openalex.org/W2384611437","https://openalex.org/W2347873412"],"abstract_inverted_index":{"This":[0,33],"paper":[1],"describes":[2],"a":[3,24],"32\u00d732b":[4],"4-read":[5],"2-write":[6],"ported":[7],"register":[8],"file":[9],"in":[10,55],"65nm":[11],"CMOS.":[12],"A":[13],"single-ended":[14],"read":[15,26,30,34,47,56,61,87,103,121,133],"cell":[16,68],"using":[17],"pass":[18],"gate":[19],"is":[20,53,70,113,125,135],"proposed,":[21],"which":[22,58,99],"supports":[23],"static":[25,62],"access":[27],"on":[28,45,85],"the":[29,46,60,83,86,132],"bit":[31,48,88],"line.":[32,49],"scheme":[35],"avoids":[36],"switching":[37],"power":[38,104,109,119,140,145],"when":[39,120],"successive":[40],"\u201c0\u201d":[41],"or":[42,122],"\u201c1\u201d":[43],"emerges":[44],"An":[50],"inverter":[51],"isolator":[52],"added":[54],"port,":[57],"improves":[59],"noise":[63],"margin":[64],"(SNM)":[65],"dramatically.":[66],"The":[67],"array":[69],"divided":[71],"into":[72],"4":[73],"banks":[74],"with":[75,137],"each":[76],"bank":[77],"8":[78],"words.":[79],"In":[80],"this":[81],"way,":[82],"capacities":[84],"line":[89],"are":[90],"cut":[91,116],"down":[92],"to":[93,115],"25%":[94],"of":[95],"that":[96,131],"not":[97,126],"banked,":[98],"benefits":[100],"for":[101],"both":[102],"and":[105,141],"latency.":[106],"To":[107],"reduce":[108],"further,":[110],"clock":[111],"gating":[112],"used":[114],"off":[117],"active":[118],"write":[123],"operation":[124],"necessary.":[127],"Simulation":[128],"results":[129],"show":[130],"latency":[134],"1.06ns":[136],"12mW":[138],"total":[139],"18":[142],"uW":[143],"leakage":[144],"at":[146],"1.2V.":[147]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
