{"id":"https://openalex.org/W1966158565","doi":"https://doi.org/10.1109/asicon.2011.6157171","title":"A software/hardware co-debug platform for multi-core systems","display_name":"A software/hardware co-debug platform for multi-core systems","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W1966158565","doi":"https://doi.org/10.1109/asicon.2011.6157171","mag":"1966158565"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2011.6157171","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157171","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5079657769","display_name":"Kuen-Jong Lee","orcid":"https://orcid.org/0000-0002-6690-0074"},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Kuen-Jong Lee","raw_affiliation_strings":["Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","Department of Electrical Engineering, National Cheng Kung University, Tainan (Taiwan)"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","institution_ids":["https://openalex.org/I91807558"]},{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan (Taiwan)","institution_ids":["https://openalex.org/I91807558"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091172510","display_name":"Alan P. Su","orcid":"https://orcid.org/0000-0002-5735-7700"},"institutions":[{"id":"https://openalex.org/I4210086231","display_name":"Global Unichip (Taiwan)","ror":"https://ror.org/00005jn19","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210086231"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Alan Su","raw_affiliation_strings":["Global UniChip Corporation, HsinChu, Taiwan",", Global Unichip Corporation, Hsinchu, Taiwan#TAB#"],"affiliations":[{"raw_affiliation_string":"Global UniChip Corporation, HsinChu, Taiwan","institution_ids":["https://openalex.org/I4210086231"]},{"raw_affiliation_string":", Global Unichip Corporation, Hsinchu, Taiwan#TAB#","institution_ids":["https://openalex.org/I4210086231"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111522106","display_name":"Long-Feng Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Long-Feng Chen","raw_affiliation_strings":["Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","Department of Electrical Engineering, National Cheng Kung University, Tainan (Taiwan)"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","institution_ids":["https://openalex.org/I91807558"]},{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan (Taiwan)","institution_ids":["https://openalex.org/I91807558"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067357078","display_name":"Jia-Wei Jhou","orcid":"https://orcid.org/0000-0002-0704-0529"},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jia-Wei Jhou","raw_affiliation_strings":["Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","Department of Electrical Engineering, National Cheng Kung University, Tainan (Taiwan)"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","institution_ids":["https://openalex.org/I91807558"]},{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan (Taiwan)","institution_ids":["https://openalex.org/I91807558"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006969216","display_name":"Jiff Kuo","orcid":null},"institutions":[{"id":"https://openalex.org/I4210086231","display_name":"Global Unichip (Taiwan)","ror":"https://ror.org/00005jn19","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210086231"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jiff Kuo","raw_affiliation_strings":["Global UniChip Corporation, HsinChu, Taiwan",", Global Unichip Corporation, Hsinchu, Taiwan#TAB#"],"affiliations":[{"raw_affiliation_string":"Global UniChip Corporation, HsinChu, Taiwan","institution_ids":["https://openalex.org/I4210086231"]},{"raw_affiliation_string":", Global Unichip Corporation, Hsinchu, Taiwan#TAB#","institution_ids":["https://openalex.org/I4210086231"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101992160","display_name":"Mark Liu","orcid":"https://orcid.org/0000-0002-9896-5753"},"institutions":[{"id":"https://openalex.org/I4210086231","display_name":"Global Unichip (Taiwan)","ror":"https://ror.org/00005jn19","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210086231"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Mark Liu","raw_affiliation_strings":["Global UniChip Corporation, HsinChu, Taiwan",", Global Unichip Corporation, Hsinchu, Taiwan#TAB#"],"affiliations":[{"raw_affiliation_string":"Global UniChip Corporation, HsinChu, Taiwan","institution_ids":["https://openalex.org/I4210086231"]},{"raw_affiliation_string":", Global Unichip Corporation, Hsinchu, Taiwan#TAB#","institution_ids":["https://openalex.org/I4210086231"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5079657769"],"corresponding_institution_ids":["https://openalex.org/I91807558"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.05373676,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"259","last_page":"262"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.8894127607345581},{"id":"https://openalex.org/keywords/background-debug-mode-interface","display_name":"Background debug mode interface","score":0.7914096713066101},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7911496162414551},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6768393516540527},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.599723219871521},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5558628439903259},{"id":"https://openalex.org/keywords/software-prototyping","display_name":"Software prototyping","score":0.4566369354724884},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4397008419036865},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.42630505561828613},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.41294485330581665},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3771597445011139},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.31128519773483276},{"id":"https://openalex.org/keywords/software-development","display_name":"Software development","score":0.305792897939682}],"concepts":[{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.8894127607345581},{"id":"https://openalex.org/C124774103","wikidata":"https://www.wikidata.org/wiki/Q4839640","display_name":"Background debug mode interface","level":3,"score":0.7914096713066101},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7911496162414551},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6768393516540527},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.599723219871521},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5558628439903259},{"id":"https://openalex.org/C2776697782","wikidata":"https://www.wikidata.org/wiki/Q576460","display_name":"Software prototyping","level":4,"score":0.4566369354724884},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4397008419036865},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.42630505561828613},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.41294485330581665},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3771597445011139},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.31128519773483276},{"id":"https://openalex.org/C529173508","wikidata":"https://www.wikidata.org/wiki/Q638608","display_name":"Software development","level":3,"score":0.305792897939682}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2011.6157171","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157171","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.4399999976158142}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1567646530","https://openalex.org/W2068239131","https://openalex.org/W2120294448","https://openalex.org/W2129629918","https://openalex.org/W2141577907","https://openalex.org/W2148960378","https://openalex.org/W2162925013","https://openalex.org/W2167570136","https://openalex.org/W6678227370"],"related_works":["https://openalex.org/W2361273971","https://openalex.org/W2351581202","https://openalex.org/W2978026406","https://openalex.org/W2385068581","https://openalex.org/W2381166695","https://openalex.org/W4241045879","https://openalex.org/W2366346238","https://openalex.org/W2388687068","https://openalex.org/W2366922255","https://openalex.org/W2993910401"],"abstract_inverted_index":{"In":[0],"this":[1,68,115],"paper":[2],"we":[3],"present":[4],"a":[5,71,88,105],"software/hardware":[6],"co-debug":[7],"platform":[8,24,116],"to":[9,27,93],"deal":[10],"with":[11,20,128],"the":[12,37,95,110,119],"various":[13,47,84],"debug":[14,28,73,81,96],"problems":[15],"in":[16,117],"multiple-core":[17,125],"SOC":[18,126],"systems":[19,127],"multiple-clock":[21,129],"domains.":[22,130],"This":[23],"allows":[25],"designers":[26],"embedded":[29],"processors,":[30],"buses,":[31],"IP":[32],"cores,":[33],"as":[34,36],"well":[35],"application":[38],"programs":[39],"being":[40],"developed.":[41],"It":[42],"can":[43],"be":[44],"used":[45],"at":[46],"design":[48],"and":[49,59,87,100,112],"manufacturing":[50],"stages":[51],"including":[52],"component":[53],"development,":[54],"hardware/software":[55],"co-design,":[56],"system":[57],"prototyping,":[58],"post-silicon":[60],"debugging.":[61],"Three":[62],"major":[63],"mechanisms":[64],"are":[65],"integrated":[66],"into":[67],"platform,":[69],"namely":[70],"software":[72,99],"mechanism":[74,82,92],"for":[75,83,124],"multi-core":[76],"programming,":[77],"an":[78],"on-chip":[79],"hardware":[80,85],"IPs,":[86],"two-way":[89],"cross":[90],"trigger":[91],"synchronize":[94],"processes":[97],"of":[98,114,122],"hardware.":[101],"Experimental":[102],"results":[103],"on":[104],"FPGA":[106],"prototyping":[107],"board":[108],"demonstrate":[109],"effectiveness":[111],"efficiency":[113],"identifying":[118],"root":[120],"causes":[121],"failures":[123]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}