{"id":"https://openalex.org/W1973743588","doi":"https://doi.org/10.1109/asicon.2011.6157154","title":"A novel hardware prefetching scheme exploiting 2-D spatial locality in multimedia applications","display_name":"A novel hardware prefetching scheme exploiting 2-D spatial locality in multimedia applications","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W1973743588","doi":"https://doi.org/10.1109/asicon.2011.6157154","mag":"1973743588"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2011.6157154","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157154","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100778051","display_name":"Jin Huang","orcid":"https://orcid.org/0000-0002-8044-9865"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Jin Huang","raw_affiliation_strings":["School of Microelectronics, Shanghai Jiaotong University, Shanghai, China","School of Microelectronics, Shanghai Jiao Tong University, 200240, China"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Shanghai Jiaotong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]},{"raw_affiliation_string":"School of Microelectronics, Shanghai Jiao Tong University, 200240, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048603612","display_name":"Jing Xie","orcid":"https://orcid.org/0000-0003-1236-3944"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jing Xie","raw_affiliation_strings":["School of Microelectronics, Shanghai Jiaotong University, Shanghai, China","School of Microelectronics, Shanghai Jiao Tong University, 200240, China"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Shanghai Jiaotong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]},{"raw_affiliation_string":"School of Microelectronics, Shanghai Jiao Tong University, 200240, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103236320","display_name":"Zhigang Mao","orcid":"https://orcid.org/0000-0001-9431-9853"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhigang Mao","raw_affiliation_strings":["School of Microelectronics, Shanghai Jiaotong University, Shanghai, China","School of Microelectronics, Shanghai Jiao Tong University, 200240, China"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Shanghai Jiaotong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]},{"raw_affiliation_string":"School of Microelectronics, Shanghai Jiao Tong University, 200240, China","institution_ids":["https://openalex.org/I183067930"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5100778051"],"corresponding_institution_ids":["https://openalex.org/I183067930"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.05850912,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"192","last_page":"195"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8720754384994507},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7876132726669312},{"id":"https://openalex.org/keywords/locality","display_name":"Locality","score":0.7263323664665222},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.708724319934845},{"id":"https://openalex.org/keywords/locality-of-reference","display_name":"Locality of reference","score":0.6572566032409668},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.5965637564659119},{"id":"https://openalex.org/keywords/table","display_name":"Table (database)","score":0.5878291726112366},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5016460418701172},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.4782920479774475},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.4676715135574341},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4507076144218445},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3854236900806427},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.20973053574562073},{"id":"https://openalex.org/keywords/database","display_name":"Database","score":0.17375227808952332}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8720754384994507},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7876132726669312},{"id":"https://openalex.org/C2779808786","wikidata":"https://www.wikidata.org/wiki/Q6664603","display_name":"Locality","level":2,"score":0.7263323664665222},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.708724319934845},{"id":"https://openalex.org/C27602214","wikidata":"https://www.wikidata.org/wiki/Q1868547","display_name":"Locality of reference","level":3,"score":0.6572566032409668},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.5965637564659119},{"id":"https://openalex.org/C45235069","wikidata":"https://www.wikidata.org/wiki/Q278425","display_name":"Table (database)","level":2,"score":0.5878291726112366},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5016460418701172},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.4782920479774475},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.4676715135574341},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4507076144218445},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3854236900806427},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.20973053574562073},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.17375227808952332},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2011.6157154","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157154","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W2016558956","https://openalex.org/W2049703229","https://openalex.org/W2103330947","https://openalex.org/W2111519549","https://openalex.org/W2125305952","https://openalex.org/W2139868052","https://openalex.org/W2152706327","https://openalex.org/W2294693415","https://openalex.org/W3151327929","https://openalex.org/W4229810777","https://openalex.org/W4245636261","https://openalex.org/W4255238016"],"related_works":["https://openalex.org/W1555349535","https://openalex.org/W2583128298","https://openalex.org/W2053359564","https://openalex.org/W2161159383","https://openalex.org/W1495260638","https://openalex.org/W1511204342","https://openalex.org/W2369125128","https://openalex.org/W2369223577","https://openalex.org/W2527471267","https://openalex.org/W1534408758"],"abstract_inverted_index":{"Standard":[0],"cache":[1,30,100],"memories":[2,31],"exploit":[3],"1-D":[4],"spatial":[5],"locality":[6],"which":[7,44],"will":[8],"suffer":[9],"great":[10],"performance":[11],"penalty":[12],"when":[13],"applied":[14],"to":[15,28,32,67,105],"multimedia":[16,33],"that":[17,91],"manifests":[18],"2-D":[19],"data":[20,63,92],"dependence.":[21],"History-based":[22],"prefetching":[23,72],"policies":[24],"have":[25],"been":[26],"proposed":[27],"tailor":[29],"applications.":[34],"Such":[35],"schemes,":[36],"however,":[37],"are":[38],"driven":[39],"by":[40,103],"the":[41],"instruction":[42,54],"address,":[43],"means":[45],"it":[46],"needs":[47],"a":[48,61,109],"significantly":[49,98],"large":[50],"prediction":[51,111],"table":[52],"for":[53],"caching.":[55],"In":[56],"this":[57],"paper":[58],"we":[59],"propose":[60],"novel":[62],"address":[64,93],"directed":[65,94],"scheme":[66,73],"pure":[68],"hardware":[69],"prefetching.":[70],"The":[71,87],"is":[74],"modeled":[75],"and":[76],"evaluated":[77],"at":[78],"transaction":[79],"level":[80],"(TLM)":[81],"based":[82],"on":[83],"Carbon":[84],"SoC":[85],"Designer.":[86],"experimental":[88],"results":[89],"show":[90],"prefetching-on-miss":[95],"policy":[96],"can":[97],"reduce":[99],"miss":[101],"rate":[102],"up":[104],"23.8%":[106],"with":[107],"only":[108],"small":[110],"table.":[112]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
