{"id":"https://openalex.org/W2054237707","doi":"https://doi.org/10.1109/asicon.2011.6157146","title":"Design and verification of an application-specific PLD using VHDL and SystemVerilog","display_name":"Design and verification of an application-specific PLD using VHDL and SystemVerilog","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W2054237707","doi":"https://doi.org/10.1109/asicon.2011.6157146","mag":"2054237707"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2011.6157146","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157146","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100767181","display_name":"Jae\u2010Jin Lee","orcid":"https://orcid.org/0000-0003-3260-1620"},"institutions":[{"id":"https://openalex.org/I142401562","display_name":"Electronics and Telecommunications Research Institute","ror":"https://ror.org/03ysstz10","country_code":"KR","type":"facility","lineage":["https://openalex.org/I142401562","https://openalex.org/I2801339556","https://openalex.org/I4210144908","https://openalex.org/I4387152098"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Jae-Jin Lee","raw_affiliation_strings":["Electronics and Telecommunications Research Institute, Daejeon, South Korea","Electrionics and Telecommunications Reaserch Institute, 218 Gajeongno,Yuseong-gu, Deajeon, Korea"],"affiliations":[{"raw_affiliation_string":"Electronics and Telecommunications Research Institute, Daejeon, South Korea","institution_ids":["https://openalex.org/I142401562"]},{"raw_affiliation_string":"Electrionics and Telecommunications Reaserch Institute, 218 Gajeongno,Yuseong-gu, Deajeon, Korea","institution_ids":["https://openalex.org/I142401562"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101044931","display_name":"Young-Jin Oh","orcid":null},"institutions":[{"id":"https://openalex.org/I163753206","display_name":"Chungbuk National University","ror":"https://ror.org/02wnxgj78","country_code":"KR","type":"education","lineage":["https://openalex.org/I163753206"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Young-Jin Oh","raw_affiliation_strings":["School of Electronics engineering College of Electrical and Computer Engineering, Chungbuk National University, Cheongju, Chungbuk, South Korea","School of Electronics engineering College of Electrical and Computer Engineering, Chungbuk National University Cheongju, Korea"],"affiliations":[{"raw_affiliation_string":"School of Electronics engineering College of Electrical and Computer Engineering, Chungbuk National University, Cheongju, Chungbuk, South Korea","institution_ids":["https://openalex.org/I163753206"]},{"raw_affiliation_string":"School of Electronics engineering College of Electrical and Computer Engineering, Chungbuk National University Cheongju, Korea","institution_ids":["https://openalex.org/I163753206"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109907991","display_name":"Gi-Yong Song","orcid":null},"institutions":[{"id":"https://openalex.org/I163753206","display_name":"Chungbuk National University","ror":"https://ror.org/02wnxgj78","country_code":"KR","type":"education","lineage":["https://openalex.org/I163753206"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Gi-Yong Song","raw_affiliation_strings":["School of Electronics engineering College of Electrical and Computer Engineering, Chungbuk National University, Cheongju, Chungbuk, South Korea","School of Electronics engineering College of Electrical and Computer Engineering, Chungbuk National University Cheongju, Korea"],"affiliations":[{"raw_affiliation_string":"School of Electronics engineering College of Electrical and Computer Engineering, Chungbuk National University, Cheongju, Chungbuk, South Korea","institution_ids":["https://openalex.org/I163753206"]},{"raw_affiliation_string":"School of Electronics engineering College of Electrical and Computer Engineering, Chungbuk National University Cheongju, Korea","institution_ids":["https://openalex.org/I163753206"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5100767181"],"corresponding_institution_ids":["https://openalex.org/I142401562"],"apc_list":null,"apc_paid":null,"fwci":0.2519,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.55311635,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"159","last_page":"162"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7588784694671631},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7413727641105652},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6367259621620178},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.49787020683288574},{"id":"https://openalex.org/keywords/systolic-array","display_name":"Systolic array","score":0.49510255455970764},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.47231361269950867},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.46880772709846497},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4538402259349823},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.41842398047447205},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.402820348739624},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.39423784613609314},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.37095439434051514},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3307909667491913},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2011171281337738}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7588784694671631},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.7413727641105652},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6367259621620178},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.49787020683288574},{"id":"https://openalex.org/C150741067","wikidata":"https://www.wikidata.org/wiki/Q2377218","display_name":"Systolic array","level":3,"score":0.49510255455970764},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.47231361269950867},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.46880772709846497},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4538402259349823},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.41842398047447205},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.402820348739624},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.39423784613609314},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.37095439434051514},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3307909667491913},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2011171281337738},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2011.6157146","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157146","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1604816148","https://openalex.org/W1994266431","https://openalex.org/W2070314832","https://openalex.org/W2079870403","https://openalex.org/W2095499572","https://openalex.org/W3202711792","https://openalex.org/W4210448712"],"related_works":["https://openalex.org/W1917852300","https://openalex.org/W2384838054","https://openalex.org/W2548456620","https://openalex.org/W2139058049","https://openalex.org/W2376018793","https://openalex.org/W2075214143","https://openalex.org/W108975065","https://openalex.org/W2491368619","https://openalex.org/W2363829830","https://openalex.org/W2115658098"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,10,25,109],"new":[4],"application-specific":[5,15],"PLD":[6,48,66,105],"architecture":[7,49],"which":[8],"adopts":[9],"bit-level":[11,34],"super-systolic":[12,35],"array":[13,36,42],"for":[14,45],"arithmetic":[16],"operation":[17],"such":[18],"as":[19,58],"MAC.":[20],"The":[21,33,80],"proposed":[22,47,104],"design":[23],"offers":[24],"significant":[26],"alternative":[27],"view":[28],"on":[29,102],"programmable":[30],"logic":[31],"device.":[32],"whose":[37],"cell":[38],"contains":[39],"another":[40],"systolic":[41],"is":[43,84],"ideal":[44],"newly":[46],"in":[50,64],"terms":[51],"of":[52,96],"area":[53],"efficiency":[54],"and":[55,73,91,98],"clock":[56,82],"speed":[57],"it":[59],"limits":[60],"the":[61,65,103],"routing":[62],"requirement":[63],"to":[67,74],"local":[68],"interconnections":[69,76],"between":[70,77],"Logic":[71,78],"Units":[72],"global":[75],"Modules.":[79],"maximum":[81],"cycle":[83],"limited":[85],"only":[86],"by":[87],"one":[88,92],"AND":[89],"gate":[90],"full":[93],"adder.":[94],"Operations":[95],"convolution":[97],"FIR":[99],"filter":[100],"implemented":[101],"are":[106],"checked":[107],"using":[108],"SystemVerilog-coded":[110],"verification":[111],"platform.":[112]},"counts_by_year":[{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}