{"id":"https://openalex.org/W2009317585","doi":"https://doi.org/10.1109/asicon.2011.6157124","title":"A new configurable logic block with 4/5-input configurable LUT and fast/slow-path carry chain","display_name":"A new configurable logic block with 4/5-input configurable LUT and fast/slow-path carry chain","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W2009317585","doi":"https://doi.org/10.1109/asicon.2011.6157124","mag":"2009317585"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2011.6157124","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157124","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030667456","display_name":"Zhidong Mao","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Zhidong Mao","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","State-Key Lab of ASIC and System, Fudan University, Shanghai 201203, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State-Key Lab of ASIC and System, Fudan University, Shanghai 201203, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5107145124","display_name":"Liguang Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Liguang Chen","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","State-Key Lab of ASIC and System, Fudan University, Shanghai 201203, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State-Key Lab of ASIC and System, Fudan University, Shanghai 201203, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002438548","display_name":"Yuan Wang","orcid":"https://orcid.org/0000-0002-4951-4286"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuan Wang","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","State-Key Lab of ASIC and System, Fudan University, Shanghai 201203, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State-Key Lab of ASIC and System, Fudan University, Shanghai 201203, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081419061","display_name":"Jinmei Lai","orcid":"https://orcid.org/0009-0003-5238-4720"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinmei Lai","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","State-Key Lab of ASIC and System, Fudan University, Shanghai 201203, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State-Key Lab of ASIC and System, Fudan University, Shanghai 201203, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5030667456"],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.07670506,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"67","last_page":"70"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.812653660774231},{"id":"https://openalex.org/keywords/carry","display_name":"Carry (investment)","score":0.7562366127967834},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7240712642669678},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5536459684371948},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5294228196144104},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.5281156301498413},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.5122708678245544},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5005245208740234},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.49974489212036133},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4861406981945038},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.46938273310661316},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4692796468734741},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.45356178283691406},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.44753551483154297},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.41887611150741577},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.2595273554325104},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.19771674275398254},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.19580966234207153},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.17864152789115906},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.16996362805366516},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13315442204475403},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10101005434989929}],"concepts":[{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.812653660774231},{"id":"https://openalex.org/C2776299755","wikidata":"https://www.wikidata.org/wiki/Q432449","display_name":"Carry (investment)","level":2,"score":0.7562366127967834},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7240712642669678},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5536459684371948},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5294228196144104},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.5281156301498413},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.5122708678245544},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5005245208740234},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.49974489212036133},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4861406981945038},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.46938273310661316},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4692796468734741},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.45356178283691406},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.44753551483154297},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.41887611150741577},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.2595273554325104},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.19771674275398254},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.19580966234207153},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.17864152789115906},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.16996362805366516},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13315442204475403},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10101005434989929},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C10138342","wikidata":"https://www.wikidata.org/wiki/Q43015","display_name":"Finance","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2011.6157124","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157124","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2045726766","https://openalex.org/W2113645429","https://openalex.org/W6662167024"],"related_works":["https://openalex.org/W2003435315","https://openalex.org/W2098419840","https://openalex.org/W2016936938","https://openalex.org/W2053477566","https://openalex.org/W2526300902","https://openalex.org/W2149339590","https://openalex.org/W2125567818","https://openalex.org/W1553855433","https://openalex.org/W1827076955","https://openalex.org/W1990901299"],"abstract_inverted_index":{"A":[0],"new":[1,48],"LUT":[2,17,78],"and":[3,24,54,79],"carry":[4,49,56,83],"structure":[5,51],"embedded":[6],"in":[7,62,82],"the":[8,39],"configurable":[9],"logic":[10],"block":[11],"of":[12,41,76,85],"FPGA":[13],"is":[14,18,60],"proposed.":[15],"The":[16,58,69],"designed":[19],"to":[20,34],"support":[21],"both":[22],"4-input":[23],"5-input":[25],"structures,":[26],"which":[27],"can":[28],"be":[29],"configured":[30],"by":[31],"users":[32],"according":[33],"their":[35],"needs":[36],"without":[37],"increasing":[38],"complexity":[40],"interconnect":[42],"structures.":[43],"We":[44],"also":[45],"develop":[46],"a":[47,73,80],"chain":[50],"with":[52],"fast":[53],"slow":[55],"paths.":[57],"circuit":[59],"fabricated":[61],"0.13um":[63],"1P8M":[64],"1.2/2.5/3.3V":[65],"Logic":[66],"CMOS":[67],"technology.":[68],"measured":[70],"results":[71],"show":[72],"correct":[74],"function":[75],"4/5-input":[77],"speedup":[81],"performance":[84],"nearly":[86],"3":[87],"times":[88],"over":[89],"current":[90],"architecture.":[91]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
