{"id":"https://openalex.org/W2048159764","doi":"https://doi.org/10.1109/asicon.2011.6157114","title":"Scheduling to timing optimization for a novel high-level synthesis approach","display_name":"Scheduling to timing optimization for a novel high-level synthesis approach","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W2048159764","doi":"https://doi.org/10.1109/asicon.2011.6157114","mag":"2048159764"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2011.6157114","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157114","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037788925","display_name":"Ling Li","orcid":"https://orcid.org/0000-0001-9722-9503"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Ling Li","raw_affiliation_strings":["Key Laboratory of Integrated Microsystem, Peking University Shenzhen Graduate School, Shenzhen, China","Key Lab of Integrated Microsystem, Peking University Shenzhen Graduate School, 518055, China"],"affiliations":[{"raw_affiliation_string":"Key Laboratory of Integrated Microsystem, Peking University Shenzhen Graduate School, Shenzhen, China","institution_ids":["https://openalex.org/I20231570"]},{"raw_affiliation_string":"Key Lab of Integrated Microsystem, Peking University Shenzhen Graduate School, 518055, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100348960","display_name":"Teng Wang","orcid":"https://orcid.org/0000-0003-3067-4674"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Teng Wang","raw_affiliation_strings":["Key Laboratory of Integrated Microsystem, Peking University Shenzhen Graduate School, Shenzhen, China","Key Lab of Integrated Microsystem, Peking University Shenzhen Graduate School, 518055, China"],"affiliations":[{"raw_affiliation_string":"Key Laboratory of Integrated Microsystem, Peking University Shenzhen Graduate School, Shenzhen, China","institution_ids":["https://openalex.org/I20231570"]},{"raw_affiliation_string":"Key Lab of Integrated Microsystem, Peking University Shenzhen Graduate School, 518055, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102171012","display_name":"Ziyi Hu","orcid":null},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ziyi Hu","raw_affiliation_strings":["Key Laboratory of Integrated Microsystem, Peking University Shenzhen Graduate School, Shenzhen, China","Key Lab of Integrated Microsystem, Peking University Shenzhen Graduate School, 518055, China"],"affiliations":[{"raw_affiliation_string":"Key Laboratory of Integrated Microsystem, Peking University Shenzhen Graduate School, Shenzhen, China","institution_ids":["https://openalex.org/I20231570"]},{"raw_affiliation_string":"Key Lab of Integrated Microsystem, Peking University Shenzhen Graduate School, 518055, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102009436","display_name":"Xinan Wang","orcid":"https://orcid.org/0000-0003-1458-8258"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xin'an Wang","raw_affiliation_strings":["Key Laboratory of Integrated Microsystem, Peking University Shenzhen Graduate School, Shenzhen, China","Key Lab of Integrated Microsystem, Peking University Shenzhen Graduate School, 518055, China"],"affiliations":[{"raw_affiliation_string":"Key Laboratory of Integrated Microsystem, Peking University Shenzhen Graduate School, Shenzhen, China","institution_ids":["https://openalex.org/I20231570"]},{"raw_affiliation_string":"Key Lab of Integrated Microsystem, Peking University Shenzhen Graduate School, 518055, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066780326","display_name":"Xu Zhang","orcid":"https://orcid.org/0009-0009-0027-9818"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xu Zhang","raw_affiliation_strings":["Key Laboratory of Integrated Microsystem, Peking University Shenzhen Graduate School, Shenzhen, China","Key Lab of Integrated Microsystem, Peking University Shenzhen Graduate School, 518055, China"],"affiliations":[{"raw_affiliation_string":"Key Laboratory of Integrated Microsystem, Peking University Shenzhen Graduate School, Shenzhen, China","institution_ids":["https://openalex.org/I20231570"]},{"raw_affiliation_string":"Key Lab of Integrated Microsystem, Peking University Shenzhen Graduate School, 518055, China","institution_ids":["https://openalex.org/I20231570"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5037788925"],"corresponding_institution_ids":["https://openalex.org/I20231570"],"apc_list":null,"apc_paid":null,"fwci":0.2519,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.54987115,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"29","last_page":"32"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/operand","display_name":"Operand","score":0.8839017748832703},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.7390181422233582},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7045261263847351},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6385652422904968},{"id":"https://openalex.org/keywords/operator","display_name":"Operator (biology)","score":0.6242423057556152},{"id":"https://openalex.org/keywords/processor-scheduling","display_name":"Processor scheduling","score":0.4674922525882721},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.4563463628292084},{"id":"https://openalex.org/keywords/job-shop-scheduling","display_name":"Job shop scheduling","score":0.45209863781929016},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.3910675048828125},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3029323220252991},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.18199408054351807},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.17084237933158875},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16449257731437683},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.08705860376358032},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08649811148643494},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07624179124832153}],"concepts":[{"id":"https://openalex.org/C55526617","wikidata":"https://www.wikidata.org/wiki/Q719375","display_name":"Operand","level":2,"score":0.8839017748832703},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.7390181422233582},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7045261263847351},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6385652422904968},{"id":"https://openalex.org/C17020691","wikidata":"https://www.wikidata.org/wiki/Q139677","display_name":"Operator (biology)","level":5,"score":0.6242423057556152},{"id":"https://openalex.org/C2984822820","wikidata":"https://www.wikidata.org/wiki/Q1123036","display_name":"Processor scheduling","level":3,"score":0.4674922525882721},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.4563463628292084},{"id":"https://openalex.org/C55416958","wikidata":"https://www.wikidata.org/wiki/Q6206757","display_name":"Job shop scheduling","level":3,"score":0.45209863781929016},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.3910675048828125},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3029323220252991},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.18199408054351807},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.17084237933158875},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16449257731437683},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.08705860376358032},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08649811148643494},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07624179124832153},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.0},{"id":"https://openalex.org/C86339819","wikidata":"https://www.wikidata.org/wiki/Q407384","display_name":"Transcription factor","level":3,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C158448853","wikidata":"https://www.wikidata.org/wiki/Q425218","display_name":"Repressor","level":4,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2011.6157114","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2011.6157114","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 9th IEEE International Conference on ASIC","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.41999998688697815,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1577039630","https://openalex.org/W1986207994","https://openalex.org/W1992590229","https://openalex.org/W2015310144","https://openalex.org/W2025752838","https://openalex.org/W2033893025","https://openalex.org/W2060342326","https://openalex.org/W2063747323","https://openalex.org/W2087376924","https://openalex.org/W2093842169","https://openalex.org/W2095672647","https://openalex.org/W2101981435","https://openalex.org/W2134963129","https://openalex.org/W2152531251","https://openalex.org/W4206153422","https://openalex.org/W4230257272","https://openalex.org/W4232535952","https://openalex.org/W4253257278","https://openalex.org/W6666553449"],"related_works":["https://openalex.org/W4250699891","https://openalex.org/W2048159764","https://openalex.org/W2530146034","https://openalex.org/W2145890695","https://openalex.org/W4239976916","https://openalex.org/W2153937041","https://openalex.org/W1490270176","https://openalex.org/W1976754731","https://openalex.org/W2073831404","https://openalex.org/W2537224470"],"abstract_inverted_index":{"Traditional":[0],"IC":[1,28],"design":[2,12,42,57,92],"methodology":[3],"based":[4,65],"on":[5,11,66],"standard":[6],"cells":[7],"shows":[8],"its":[9],"limitation":[10],"efficiency,":[13],"which":[14,61],"can":[15],"not":[16],"satisfy":[17],"the":[18,67,70,73,78,84,87,90],"needs":[19],"for":[20,55],"shorter":[21],"time-to-market":[22],"and":[23,75,86,94,101],"more":[24],"advanced":[25],"functionality":[26],"of":[27,69,77,89,109,112],"products.":[29],"To":[30],"solve":[31],"this":[32,47],"problem,":[33],"a":[34,49,96],"novel":[35],"high":[36],"level":[37],"synthesis":[38],"method":[39,43,58],"named":[40],"operator":[41,56,91],"is":[44,59,62],"proposed.":[45],"In":[46],"paper,":[48],"scheduling":[50],"scheme":[51],"to":[52],"timing":[53],"optimization":[54],"proposed,":[60],"carried":[63],"out":[64],"attributes":[68],"operand":[71],"in":[72,104],"operation":[74],"dependence":[76],"operations.":[79],"The":[80],"experiment":[81],"results":[82],"proves":[83],"feasibility":[85],"efficiency":[88],"method,":[93],"obtains":[95],"65%":[97],"faster":[98],"data-processing":[99],"capacity":[100],"30%":[102],"reduction":[103],"hardware":[105],"cost":[106],"than":[107],"that":[108],"SPARK":[110],"tool":[111],"University":[113],"California":[114],"at":[115],"San":[116],"Diego.":[117]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}