{"id":"https://openalex.org/W2051082990","doi":"https://doi.org/10.1109/ase.2011.6100049","title":"Safe asynchronous multicore memory operations","display_name":"Safe asynchronous multicore memory operations","publication_year":2011,"publication_date":"2011-11-01","ids":{"openalex":"https://openalex.org/W2051082990","doi":"https://doi.org/10.1109/ase.2011.6100049","mag":"2051082990"},"language":"en","primary_location":{"id":"doi:10.1109/ase.2011.6100049","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ase.2011.6100049","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 26th IEEE/ACM International Conference on Automated Software Engineering (ASE 2011)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5061934270","display_name":"Matko Botin\u010dan","orcid":null},"institutions":[{"id":"https://openalex.org/I241749","display_name":"University of Cambridge","ror":"https://ror.org/013meh722","country_code":"GB","type":"education","lineage":["https://openalex.org/I241749"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Matko Botincan","raw_affiliation_strings":["University of Cambridge, UK","Univ. Of Cambridge, UK"],"affiliations":[{"raw_affiliation_string":"University of Cambridge, UK","institution_ids":["https://openalex.org/I241749"]},{"raw_affiliation_string":"Univ. Of Cambridge, UK","institution_ids":["https://openalex.org/I241749"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085860278","display_name":"Mike Dodds","orcid":"https://orcid.org/0000-0002-4439-0130"},"institutions":[{"id":"https://openalex.org/I241749","display_name":"University of Cambridge","ror":"https://ror.org/013meh722","country_code":"GB","type":"education","lineage":["https://openalex.org/I241749"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Mike Dodds","raw_affiliation_strings":["University of Cambridge, UK","Univ. Of Cambridge, UK"],"affiliations":[{"raw_affiliation_string":"University of Cambridge, UK","institution_ids":["https://openalex.org/I241749"]},{"raw_affiliation_string":"Univ. Of Cambridge, UK","institution_ids":["https://openalex.org/I241749"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080781439","display_name":"Alastair F. Donaldson","orcid":"https://orcid.org/0000-0002-7448-7961"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Alastair F. Donaldson","raw_affiliation_strings":["Imperial College London, UK","Imperial College , London, UK"],"affiliations":[{"raw_affiliation_string":"Imperial College London, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Imperial College , London, UK","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001725251","display_name":"Matthew Parkinson","orcid":"https://orcid.org/0009-0004-3937-1260"},"institutions":[{"id":"https://openalex.org/I4210164937","display_name":"Microsoft Research (United Kingdom)","ror":"https://ror.org/05k87vq12","country_code":"GB","type":"company","lineage":["https://openalex.org/I1290206253","https://openalex.org/I4210164937"]},{"id":"https://openalex.org/I1290206253","display_name":"Microsoft (United States)","ror":"https://ror.org/00d0nc645","country_code":"US","type":"company","lineage":["https://openalex.org/I1290206253"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"Matthew J. Parkinson","raw_affiliation_strings":["Microsoft Research Cambridge, UK","Microsoft Research, Cambridge, UK;"],"affiliations":[{"raw_affiliation_string":"Microsoft Research Cambridge, UK","institution_ids":["https://openalex.org/I4210164937"]},{"raw_affiliation_string":"Microsoft Research, Cambridge, UK;","institution_ids":["https://openalex.org/I1290206253"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5061934270"],"corresponding_institution_ids":["https://openalex.org/I241749"],"apc_list":null,"apc_paid":null,"fwci":1.0307,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.77939416,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"153","last_page":"162"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10126","display_name":"Logic, programming, and type systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.85100257396698},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.678486704826355},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.5799130201339722},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5154832005500793},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.46185362339019775},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.41647887229919434},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.41596442461013794},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.37006330490112305}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.85100257396698},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.678486704826355},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.5799130201339722},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5154832005500793},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.46185362339019775},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.41647887229919434},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.41596442461013794},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.37006330490112305},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/ase.2011.6100049","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ase.2011.6100049","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 26th IEEE/ACM International Conference on Automated Software Engineering (ASE 2011)","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.225.1737","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.225.1737","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://web.math.hr/%7Emabotinc/downloads/ase2011.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.227.6355","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.227.6355","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cl.cam.ac.uk/%7Emd466/publications/ASE.11.safe_async.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Peace, Justice and strong institutions","id":"https://metadata.un.org/sdg/16","score":0.8199999928474426}],"awards":[{"id":"https://openalex.org/G1322032678","display_name":null,"funder_award_id":"EP/H010815/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G2705848627","display_name":null,"funder_award_id":"EP/G051100/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320320005","display_name":"Royal Academy of Engineering","ror":"https://ror.org/0526snb40"},{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":38,"referenced_works":["https://openalex.org/W1048515","https://openalex.org/W1508811155","https://openalex.org/W1518247129","https://openalex.org/W1549217957","https://openalex.org/W1562865234","https://openalex.org/W1564750950","https://openalex.org/W1811204973","https://openalex.org/W1972544179","https://openalex.org/W1991246212","https://openalex.org/W2043100293","https://openalex.org/W2053154567","https://openalex.org/W2061341742","https://openalex.org/W2120162396","https://openalex.org/W2122799300","https://openalex.org/W2130162474","https://openalex.org/W2133662847","https://openalex.org/W2137628566","https://openalex.org/W2137818578","https://openalex.org/W2140865947","https://openalex.org/W2149984854","https://openalex.org/W2154985136","https://openalex.org/W2157877604","https://openalex.org/W2159595840","https://openalex.org/W2160536499","https://openalex.org/W2168876927","https://openalex.org/W3006363542","https://openalex.org/W3015951847","https://openalex.org/W4256028745","https://openalex.org/W4300810260","https://openalex.org/W6600049303","https://openalex.org/W6630700474","https://openalex.org/W6630957242","https://openalex.org/W6632855245","https://openalex.org/W6633422237","https://openalex.org/W6666025964","https://openalex.org/W6679329746","https://openalex.org/W6680355397","https://openalex.org/W6683781998"],"related_works":["https://openalex.org/W1998013902","https://openalex.org/W2172051598","https://openalex.org/W3023876411","https://openalex.org/W2550108858","https://openalex.org/W4205439893","https://openalex.org/W123152114","https://openalex.org/W1781968824","https://openalex.org/W4247993032","https://openalex.org/W3145476088","https://openalex.org/W2117274229"],"abstract_inverted_index":{"Asynchronous":[0],"memory":[1,10,44,67],"operations":[2,39],"provide":[3],"a":[4,52,83,136],"means":[5],"for":[6,48,56],"coping":[7],"with":[8,74],"the":[9,25,34,97,123,142],"wall":[11],"problem":[12],"in":[13,19,96],"multicore":[14,62],"processors,":[15],"and":[16,22,30,54,59,76,108,115],"are":[17],"available":[18],"many":[20],"platforms":[21],"languages,":[23],"e.g.,":[24],"Cell":[26,144],"Broadband":[27],"Engine,":[28],"CUDA":[29],"OpenCL.":[31],"Reasoning":[32],"about":[33,106],"correct":[35],"usage":[36],"of":[37,43,61,99,111,117,125,132,138],"such":[38],"involves":[40],"complex":[41],"analysis":[42],"accesses":[45],"to":[46,91],"check":[47],"races.":[49],"We":[50,87,121],"present":[51],"method":[53],"tool":[55,78],"proving":[57],"memory-safety":[58],"race-freedom":[60],"programs":[63,139],"that":[64,94],"use":[65],"asynchronous":[66],"operations.":[68],"Our":[69],"approach":[70,127],"uses":[71],"separation":[72],"logic":[73],"permissions,":[75],"our":[77,89,126],"automates":[79],"this":[80,100],"method,":[81],"targeting":[82],"C-like":[84],"core":[85],"language.":[86],"describe":[88],"solutions":[90],"several":[92],"challenges":[93],"arose":[95],"course":[98],"research.":[101],"These":[102],"include:":[103],"syntactic":[104],"reasoning":[105],"permissions":[107],"arrays,":[109],"integration":[110],"numerical":[112],"abstract":[113],"domains,":[114],"utilization":[116],"an":[118],"SMT":[119],"solver.":[120],"demonstrate":[122],"feasibility":[124],"experimentally":[128],"by":[129],"checking":[130],"absence":[131],"DMA":[133],"races":[134],"on":[135],"set":[137],"drawn":[140],"from":[141],"IBM":[143],"SDK.":[145]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2014,"cited_by_count":3}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
