{"id":"https://openalex.org/W2889426436","doi":"https://doi.org/10.1109/asap.2018.8445100","title":"Performance Estimation of Deeply Pipelined Fluid Simulation on Multiple FPGAs with High-speed Communication Subsystem","display_name":"Performance Estimation of Deeply Pipelined Fluid Simulation on Multiple FPGAs with High-speed Communication Subsystem","publication_year":2018,"publication_date":"2018-07-01","ids":{"openalex":"https://openalex.org/W2889426436","doi":"https://doi.org/10.1109/asap.2018.8445100","mag":"2889426436"},"language":"en","primary_location":{"id":"doi:10.1109/asap.2018.8445100","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2018.8445100","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5017640688","display_name":"Antoniette Mondigo","orcid":"https://orcid.org/0000-0003-1772-1050"},"institutions":[{"id":"https://openalex.org/I201537933","display_name":"Tohoku University","ror":"https://ror.org/01dq60k83","country_code":"JP","type":"education","lineage":["https://openalex.org/I201537933"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Antoniette Mondigo","raw_affiliation_strings":["Graduate School of Information Sciences, Tohoku University Sendai, Miyagi, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Information Sciences, Tohoku University Sendai, Miyagi, Japan","institution_ids":["https://openalex.org/I201537933"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081752237","display_name":"Kentaro Sano","orcid":"https://orcid.org/0000-0002-6681-4192"},"institutions":[{"id":"https://openalex.org/I4210129730","display_name":"RIKEN Center for Computational Science","ror":"https://ror.org/03r519674","country_code":"JP","type":"facility","lineage":["https://openalex.org/I4210110652","https://openalex.org/I4210129730"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kentaro Sano","raw_affiliation_strings":["Processor Research Team RIKEN R-CCS Kobe, Hyogo, Japan"],"affiliations":[{"raw_affiliation_string":"Processor Research Team RIKEN R-CCS Kobe, Hyogo, Japan","institution_ids":["https://openalex.org/I4210129730"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011172934","display_name":"Hiroyuki Takizawa","orcid":"https://orcid.org/0000-0003-2858-3140"},"institutions":[{"id":"https://openalex.org/I201537933","display_name":"Tohoku University","ror":"https://ror.org/01dq60k83","country_code":"JP","type":"education","lineage":["https://openalex.org/I201537933"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hirovuki Takizawa","raw_affiliation_strings":["Graduate School of Information Sciences, Tohoku University Sendai, Miyagi, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Information Sciences, Tohoku University Sendai, Miyagi, Japan","institution_ids":["https://openalex.org/I201537933"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5017640688"],"corresponding_institution_ids":["https://openalex.org/I201537933"],"apc_list":null,"apc_paid":null,"fwci":1.3137,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.79725363,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.9172862768173218},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.8246129751205444},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7841631174087524},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6570505499839783},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5407500267028809},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5103136897087097},{"id":"https://openalex.org/keywords/pipeline-transport","display_name":"Pipeline transport","score":0.5079377293586731},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.47649258375167847},{"id":"https://openalex.org/keywords/supercomputer","display_name":"Supercomputer","score":0.410108745098114},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.39370641112327576},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35614722967147827},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34767746925354004},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.09687820076942444},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09226319193840027}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.9172862768173218},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.8246129751205444},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7841631174087524},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6570505499839783},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5407500267028809},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5103136897087097},{"id":"https://openalex.org/C175309249","wikidata":"https://www.wikidata.org/wiki/Q725864","display_name":"Pipeline transport","level":2,"score":0.5079377293586731},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.47649258375167847},{"id":"https://openalex.org/C83283714","wikidata":"https://www.wikidata.org/wiki/Q121117","display_name":"Supercomputer","level":2,"score":0.410108745098114},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.39370641112327576},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35614722967147827},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34767746925354004},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.09687820076942444},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09226319193840027},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C87717796","wikidata":"https://www.wikidata.org/wiki/Q146326","display_name":"Environmental engineering","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asap.2018.8445100","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2018.8445100","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5199999809265137,"display_name":"Decent work and economic growth","id":"https://metadata.un.org/sdg/8"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2061488635","https://openalex.org/W2092633783","https://openalex.org/W2109369875","https://openalex.org/W2122862680","https://openalex.org/W2132094037","https://openalex.org/W2264331490","https://openalex.org/W2604282092","https://openalex.org/W2745429450"],"related_works":["https://openalex.org/W4380433113","https://openalex.org/W4386072068","https://openalex.org/W252339960","https://openalex.org/W2998132311","https://openalex.org/W2390529043","https://openalex.org/W2378320433","https://openalex.org/W2358343511","https://openalex.org/W2207067480","https://openalex.org/W2051877971","https://openalex.org/W1970117064"],"abstract_inverted_index":{"To":[0],"precisely":[1],"evaluate":[2],"the":[3,15,42,72,93,115,138],"sustained":[4,76,126],"performance":[5,127],"and":[6,75,108,131],"scalability":[7],"of":[8,17,32,88,128],"pipelined":[9,25],"multiple":[10],"FPGAs,":[11,43,70],"this":[12],"paper":[13],"presents":[14],"implementation":[16],"a":[18,23,30,36,60,89,101,125],"high-speed":[19],"communication":[20,57],"subsystem":[21,58],"for":[22,35,100],"deeply":[24],"stream":[26],"computing":[27],"platform.":[28],"Internally,":[29],"pipeline":[31,103,139],"hardware":[33],"modules":[34],"domain-specific":[37],"application":[38],"is":[39,64,98,121],"implemented":[40,65],"in":[41],"where":[44,71],"they":[45],"are":[46,79],"directly":[47],"connected":[48],"through":[49],"their":[50],"serial":[51],"transceiver":[52],"links.":[53],"The":[54],"necessary":[55],"inter-FPGA":[56,95],"with":[59,66,105,118,140],"flow":[61],"control":[62],"mechanism":[63],"Intel":[67],"Arria":[68],"10":[69],"resource":[73],"consumption":[74],"network":[77,96],"throughput":[78],"obtained,":[80],"which":[81],"averages":[82],"at":[83],"7.92":[84],"GB/s.":[85],"Performance":[86],"estimation":[87],"fluid":[90],"simulation":[91],"using":[92],"measured":[94],"parameters":[97],"shown":[99],"varied":[102],"depth":[104],"explored":[106],"temporal":[107],"spatial":[109],"parallel":[110],"options.":[111],"Results":[112],"show":[113],"that":[114],"proposed":[116],"platform":[117],"16":[119],"FPGAs":[120],"estimated":[122],"to":[123,143],"achieve":[124],"4.8":[129],"TFlops":[130],"may":[132],"be":[133],"scaled":[134],"further":[135],"by":[136],"deepening":[137],"even":[141],"up":[142],"128":[144],"FPGAs.":[145]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1}],"updated_date":"2026-04-21T08:09:41.155169","created_date":"2025-10-10T00:00:00"}