{"id":"https://openalex.org/W2740362576","doi":"https://doi.org/10.1109/asap.2017.7995264","title":"A Staged Memory Resource Management Method for CMP systems","display_name":"A Staged Memory Resource Management Method for CMP systems","publication_year":2017,"publication_date":"2017-07-01","ids":{"openalex":"https://openalex.org/W2740362576","doi":"https://doi.org/10.1109/asap.2017.7995264","mag":"2740362576"},"language":"en","primary_location":{"id":"doi:10.1109/asap.2017.7995264","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2017.7995264","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5085844008","display_name":"Yangguo Liu","orcid":"https://orcid.org/0000-0001-8037-8107"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Yangguo Liu","raw_affiliation_strings":["Microprocessor Research & Development Center, Peking University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Microprocessor Research & Development Center, Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101434489","display_name":"Junlin Lu","orcid":"https://orcid.org/0000-0003-1611-4937"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Junlin Lu","raw_affiliation_strings":["Microprocessor Research & Development Center, Peking University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Microprocessor Research & Development Center, Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101758077","display_name":"Dong Tong","orcid":"https://orcid.org/0000-0003-0987-6351"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Dong Tong","raw_affiliation_strings":["Microprocessor Research & Development Center, Peking University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Microprocessor Research & Development Center, Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100691552","display_name":"Xu Cheng","orcid":"https://orcid.org/0000-0002-5544-8852"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xu Cheng","raw_affiliation_strings":["Microprocessor Research & Development Center, Peking University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Microprocessor Research & Development Center, Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5085844008"],"corresponding_institution_ids":["https://openalex.org/I20231570"],"apc_list":null,"apc_paid":null,"fwci":0.2253,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.49398738,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"39","issue":null,"first_page":"91","last_page":"98"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8312973380088806},{"id":"https://openalex.org/keywords/extended-memory","display_name":"Extended memory","score":0.5268586874008179},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.5131633877754211},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.4805748462677002},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.46841517090797424},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.45245465636253357},{"id":"https://openalex.org/keywords/bandwidth-throttling","display_name":"Bandwidth throttling","score":0.43955233693122864},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.4351191520690918},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.43280139565467834},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.36554625630378723},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3250899910926819},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.2606700360774994},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.23654744029045105},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.19499504566192627},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.077191561460495}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8312973380088806},{"id":"https://openalex.org/C171675096","wikidata":"https://www.wikidata.org/wiki/Q1143380","display_name":"Extended memory","level":4,"score":0.5268586874008179},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.5131633877754211},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.4805748462677002},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.46841517090797424},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.45245465636253357},{"id":"https://openalex.org/C173061102","wikidata":"https://www.wikidata.org/wiki/Q478819","display_name":"Bandwidth throttling","level":3,"score":0.43955233693122864},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.4351191520690918},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.43280139565467834},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.36554625630378723},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3250899910926819},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.2606700360774994},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.23654744029045105},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.19499504566192627},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.077191561460495},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C131097465","wikidata":"https://www.wikidata.org/wiki/Q178898","display_name":"Gas compressor","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asap.2017.7995264","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2017.7995264","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1973980980","https://openalex.org/W2005395913","https://openalex.org/W2036853599","https://openalex.org/W2073899127","https://openalex.org/W2102871765","https://openalex.org/W2116437922","https://openalex.org/W2126570805","https://openalex.org/W2142875853","https://openalex.org/W2147657366","https://openalex.org/W2153882937","https://openalex.org/W2159908132","https://openalex.org/W2162639668","https://openalex.org/W2162838417","https://openalex.org/W2166263440","https://openalex.org/W2588551195","https://openalex.org/W3004300886","https://openalex.org/W6651715811"],"related_works":["https://openalex.org/W2587873888","https://openalex.org/W4321458411","https://openalex.org/W2354036839","https://openalex.org/W2334181344","https://openalex.org/W4293054943","https://openalex.org/W2558276258","https://openalex.org/W2155373950","https://openalex.org/W3048967625","https://openalex.org/W1575240748","https://openalex.org/W2565280077"],"abstract_inverted_index":{"Memory":[0,87],"interference":[1],"is":[2],"a":[3,19,40,59,74,85],"critical":[4],"impediment":[5],"to":[6,78],"system":[7,98,106,111],"performance":[8],"in":[9],"CMP":[10],"systems.":[11],"To":[12],"address":[13],"this":[14],"problem,":[15],"we":[16,47],"first":[17],"propose":[18],"Dynamically":[20],"Proportional":[21],"Bandwidth":[22],"Throttling":[23],"policy":[24,77],"(DPBT),":[25],"which":[26],"dynamically":[27],"throttles":[28],"back":[29],"memory-intensive":[30],"applications":[31],"based":[32],"on":[33],"their":[34],"memory":[35,43,51,69,75],"access":[36],"behavior.":[37],"DPBT":[38,65,96],"achieves":[39],"more":[41],"balance":[42],"bandwidth":[44],"partitioning.":[45,61],"Moreover,":[46],"improve":[48],"the":[49,67,80],"previous":[50],"channel":[52,70],"partitioning":[53,71],"scheme":[54,72],"by":[55,100],"integrating":[56],"it":[57],"with":[58,66],"bank":[60],"We":[62],"further":[63],"integrate":[64],"improved":[68],"and":[73,83,108],"scheduling":[76],"leverage":[79],"architecture":[81],"advantages,":[82],"present":[84],"Stage":[86],"Resource":[88],"Management":[89],"Method":[90],"(SRM).":[91],"Experimental":[92],"results":[93],"show":[94],"that":[95],"improves":[97],"throughput/fairness":[99],"13.5%/31.1%.":[101],"SRM":[102],"provides":[103],"27.1%":[104],"better":[105,110],"throughput":[107],"34.8%":[109],"fairness.":[112]},"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}