{"id":"https://openalex.org/W1580146721","doi":"https://doi.org/10.1109/asap.2015.7245694","title":"Accelerating data centers with reconfigurable logic","display_name":"Accelerating data centers with reconfigurable logic","publication_year":2015,"publication_date":"2015-07-01","ids":{"openalex":"https://openalex.org/W1580146721","doi":"https://doi.org/10.1109/asap.2015.7245694","mag":"1580146721"},"language":"en","primary_location":{"id":"doi:10.1109/asap.2015.7245694","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2015.7245694","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","raw_type":"proceedings-article"},"type":"conference-abstract","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030464643","display_name":"Derek Chiou","orcid":"https://orcid.org/0009-0008-6762-4527"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Derek Chiou","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":["https://openalex.org/A5030464643"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"1"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7545467615127563},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5538455843925476},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5537508726119995},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5049803853034973},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5037094950675964},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5001981258392334},{"id":"https://openalex.org/keywords/efficient-energy-use","display_name":"Efficient energy use","score":0.4764952063560486},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.4681221544742584},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.466420978307724},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4115734100341797},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3547855615615845},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1581421196460724},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.117637038230896},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0820435881614685}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7545467615127563},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5538455843925476},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5537508726119995},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5049803853034973},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5037094950675964},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5001981258392334},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.4764952063560486},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.4681221544742584},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.466420978307724},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4115734100341797},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3547855615615845},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1581421196460724},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.117637038230896},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0820435881614685},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asap.2015.7245694","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2015.7245694","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8899999856948853,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2147419146","https://openalex.org/W1589728323","https://openalex.org/W2135636985","https://openalex.org/W1502060307","https://openalex.org/W2197466303","https://openalex.org/W1607849496","https://openalex.org/W2462231960","https://openalex.org/W2139569078","https://openalex.org/W2170504327","https://openalex.org/W2526300902"],"abstract_inverted_index":{"Data":[0],"centers":[1],"are":[2],"a":[3],"highly":[4],"competitive":[5],"environment":[6],"that":[7],"demands":[8],"high":[9],"performance":[10],"and":[11],"energy":[12],"efficiency":[13],"and,":[14],"in":[15,41,64],"many":[16],"cases,":[17],"low":[18],"latency.":[19],"Custom":[20],"hardware":[21],"can":[22],"provide":[23],"significant":[24],"improvements":[25],"over":[26],"conventional":[27],"microprocessors":[28],"on":[29],"those":[30],"metrics.":[31],"Microsoft":[32],"has":[33],"been":[34],"investigating":[35],"the":[36,42],"use":[37],"of":[38,44,61],"reconfigurable":[39],"logic,":[40],"form":[43],"field":[45],"programmable":[46],"gate":[47],"arrays,":[48],"to":[49],"accelerate":[50],"its":[51],"data":[52],"centers.":[53],"In":[54],"this":[55,65],"talk,":[56],"I":[57],"will":[58],"describe":[59],"some":[60],"our":[62],"efforts":[63],"area.":[66]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}