{"id":"https://openalex.org/W1975905836","doi":"https://doi.org/10.1109/asap.2014.6868666","title":"Exploring DMA-assisted prefetching strategies for software caches on multicore clusters","display_name":"Exploring DMA-assisted prefetching strategies for software caches on multicore clusters","publication_year":2014,"publication_date":"2014-06-01","ids":{"openalex":"https://openalex.org/W1975905836","doi":"https://doi.org/10.1109/asap.2014.6868666","mag":"1975905836"},"language":"en","primary_location":{"id":"doi:10.1109/asap.2014.6868666","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2014.6868666","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031211716","display_name":"Christian Pinto","orcid":"https://orcid.org/0000-0001-7060-2742"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Christian Pinto","raw_affiliation_strings":["DEI Deparment, University of Bologna, Italy","DEI department, University of Bologna, Bologna, Italy"],"affiliations":[{"raw_affiliation_string":"DEI Deparment, University of Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]},{"raw_affiliation_string":"DEI department, University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043408422","display_name":"Luca Benini","orcid":"https://orcid.org/0000-0001-8068-3806"},"institutions":[{"id":"https://openalex.org/I4210151851","display_name":"Istituto Nazionale di Fisica Nucleare, Sezione di Trieste","ror":"https://ror.org/05j3snm48","country_code":"IT","type":"facility","lineage":["https://openalex.org/I160013858","https://openalex.org/I4210151851"]},{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Benini","raw_affiliation_strings":["Istituto Nazionale di Fisica Nucleare Sezione di Trieste, Trieste, Friuli-Venezia Giulia, IT","DEI department, University of Bologna, Bologna, Italy"],"affiliations":[{"raw_affiliation_string":"Istituto Nazionale di Fisica Nucleare Sezione di Trieste, Trieste, Friuli-Venezia Giulia, IT","institution_ids":["https://openalex.org/I4210151851"]},{"raw_affiliation_string":"DEI department, University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5031211716"],"corresponding_institution_ids":["https://openalex.org/I9360294"],"apc_list":null,"apc_paid":null,"fwci":0.27718137,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.57916948,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"224","last_page":"231"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8995660543441772},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6585142016410828},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6529512405395508},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.6457750797271729},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.5456020832061768},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.4776766896247864},{"id":"https://openalex.org/keywords/instruction-prefetch","display_name":"Instruction prefetch","score":0.4299521744251251},{"id":"https://openalex.org/keywords/page-cache","display_name":"Page cache","score":0.4187707304954529},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.4118489623069763},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4115588665008545},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4110148251056671},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.39477479457855225},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3921051621437073},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3404235243797302},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.09682533144950867}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8995660543441772},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6585142016410828},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6529512405395508},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.6457750797271729},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.5456020832061768},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.4776766896247864},{"id":"https://openalex.org/C133588205","wikidata":"https://www.wikidata.org/wiki/Q28455645","display_name":"Instruction prefetch","level":3,"score":0.4299521744251251},{"id":"https://openalex.org/C36340418","wikidata":"https://www.wikidata.org/wiki/Q7124288","display_name":"Page cache","level":5,"score":0.4187707304954529},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.4118489623069763},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4115588665008545},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4110148251056671},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.39477479457855225},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3921051621437073},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3404235243797302},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.09682533144950867},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/asap.2014.6868666","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2014.6868666","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors","raw_type":"proceedings-article"},{"id":"pmh:oai:cris.unibo.it:11585/424168","is_oa":false,"landing_page_url":"http://hdl.handle.net/11585/424168","pdf_url":null,"source":{"id":"https://openalex.org/S4306402579","display_name":"Archivio istituzionale della ricerca (Alma Mater Studiorum Universit\u00e0 di Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210117483","host_organization_name":"Istituto di Ematologia di Bologna","host_organization_lineage":["https://openalex.org/I4210117483"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W20471428","https://openalex.org/W1558831722","https://openalex.org/W1596544678","https://openalex.org/W1607994684","https://openalex.org/W1974927420","https://openalex.org/W2010128395","https://openalex.org/W2057995607","https://openalex.org/W2072902848","https://openalex.org/W2077790567","https://openalex.org/W2086454299","https://openalex.org/W2102409597","https://openalex.org/W2107373941","https://openalex.org/W2143285027","https://openalex.org/W2149590159","https://openalex.org/W2166121368","https://openalex.org/W2171134934","https://openalex.org/W2295099251","https://openalex.org/W3097096317","https://openalex.org/W4241166746","https://openalex.org/W4255807648","https://openalex.org/W6600827437","https://openalex.org/W6636288827"],"related_works":["https://openalex.org/W2535115842","https://openalex.org/W2116323004","https://openalex.org/W2133489088","https://openalex.org/W2118932116","https://openalex.org/W2298260853","https://openalex.org/W2741504934","https://openalex.org/W2020176098","https://openalex.org/W2396934146","https://openalex.org/W2163134761","https://openalex.org/W2136522229"],"abstract_inverted_index":{"Modern":[0],"many-core":[1],"programmable":[2],"accelerators":[3],"are":[4,75,132,168],"often":[5],"composed":[6],"by":[7,26,162],"several":[8],"computing":[9],"units":[10],"grouped":[11],"in":[12,103,114],"clusters,":[13],"with":[14,50],"a":[15,68,85,106,182],"shared":[16],"per-cluster":[17],"scratchpad":[18,37],"data":[19],"memory.":[20],"The":[21],"main":[22],"programming":[23,61,91],"challenge":[24],"imposed":[25],"these":[27],"architectures":[28],"is":[29,55,94,112],"to":[30,35,42,78,121,135,146,181,195],"hide":[31],"the":[32,90,109,117,124,127,148,156],"external":[33],"memory":[34,38,48,99,152],"on-chip":[36],"transfer":[39],"latency,":[40],"trying":[41],"overlap":[43],"as":[44,46],"much":[45],"possible":[47],"transfers":[49],"actual":[51],"computation.":[52,139],"This":[53],"problem":[54],"usually":[56],"tackled":[57],"using":[58],"complex":[59],"DMA-based":[60,177],"patterns":[62],"(e.g.":[63],"double":[64],"buffering),":[65],"which":[66],"require":[67],"heavy":[69],"refactoring":[70],"of":[71,105,126,150,159],"applications.":[72],"Software":[73],"caches":[74],"an":[76],"alternative":[77],"hand-optimized":[79],"DMA":[80],"programming.":[81],"However,":[82],"even":[83],"if":[84],"software":[86,183],"cache":[87,107,115,164,184],"can":[88,143],"reduce":[89,147],"effort,":[92],"it":[93],"still":[95],"relying":[96],"on":[97],"synchronous":[98,151],"transfers.":[100],"In":[101,171],"fact":[102],"case":[104],"miss,":[108],"new":[110],"line":[111],"copied":[113],"and":[116,154,189],"requesting":[118],"processor":[119],"has":[120],"wait":[122],"for":[123],"completion":[125],"transfer.":[128],"While":[129],"waiting,":[130],"processors":[131],"not":[133],"able":[134],"perform":[136],"any":[137],"other":[138],"Cache":[140],"lines":[141,165],"prefetching":[142,178],"be":[144],"used":[145],"number":[149],"transfers,":[153],"increase":[155],"active":[157],"time":[158],"each":[160],"processor,":[161],"loading":[163],"before":[166],"they":[167],"actually":[169],"needed.":[170],"this":[172],"work":[173],"we":[174],"explore":[175],"various":[176],"techniques":[179],"applied":[180,194],"implementation,":[185],"presenting":[186],"both":[187],"automatic":[188],"programmer":[190],"assisted":[191],"prefetch":[192],"mechanisms":[193],"computer":[196],"vision":[197],"kernels.":[198]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-02-09T09:26:11.010843","created_date":"2025-10-10T00:00:00"}