{"id":"https://openalex.org/W2073168800","doi":"https://doi.org/10.1109/asap.2013.6567559","title":"Pseudo-constant logic optimization","display_name":"Pseudo-constant logic optimization","publication_year":2013,"publication_date":"2013-06-01","ids":{"openalex":"https://openalex.org/W2073168800","doi":"https://doi.org/10.1109/asap.2013.6567559","mag":"2073168800"},"language":"en","primary_location":{"id":"doi:10.1109/asap.2013.6567559","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2013.6567559","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037618099","display_name":"Aaron Landy","orcid":"https://orcid.org/0000-0001-5727-1758"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Aaron Landy","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","Dept. of Electr. & Comput. Eng., University of Florida, Gainesville, FL, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5088031457","display_name":"Greg Stitt","orcid":"https://orcid.org/0000-0001-7159-7439"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Greg Stitt","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","Dept. of Electr. & Comput. Eng., University of Florida, Gainesville, FL, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5037618099"],"corresponding_institution_ids":["https://openalex.org/I33213144"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.12598494,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":93},"biblio":{"volume":null,"issue":null,"first_page":"99","last_page":"102"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/constant","display_name":"Constant (computer programming)","score":0.8391675353050232},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.613294243812561},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5884088277816772},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5589162707328796},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5326870083808899},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.5092283487319946},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.4603128135204315},{"id":"https://openalex.org/keywords/folding","display_name":"Folding (DSP implementation)","score":0.43414124846458435},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.34315770864486694},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.13732635974884033},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.06609711050987244},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.05648872256278992}],"concepts":[{"id":"https://openalex.org/C2777027219","wikidata":"https://www.wikidata.org/wiki/Q1284190","display_name":"Constant (computer programming)","level":2,"score":0.8391675353050232},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.613294243812561},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5884088277816772},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5589162707328796},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5326870083808899},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.5092283487319946},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.4603128135204315},{"id":"https://openalex.org/C2776545253","wikidata":"https://www.wikidata.org/wiki/Q5464292","display_name":"Folding (DSP implementation)","level":2,"score":0.43414124846458435},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.34315770864486694},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.13732635974884033},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.06609711050987244},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.05648872256278992},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asap.2013.6567559","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2013.6567559","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1895654053","https://openalex.org/W1992336996","https://openalex.org/W2101219550","https://openalex.org/W2110159903","https://openalex.org/W2124766622","https://openalex.org/W2133301618","https://openalex.org/W2147903032","https://openalex.org/W2148513374","https://openalex.org/W2150022482","https://openalex.org/W2151812287","https://openalex.org/W2154991996","https://openalex.org/W2158184698"],"related_works":["https://openalex.org/W1966764473","https://openalex.org/W2098419840","https://openalex.org/W2614722573","https://openalex.org/W2121963733","https://openalex.org/W2789349722","https://openalex.org/W1977171228","https://openalex.org/W2102927888","https://openalex.org/W4249951793","https://openalex.org/W2170504327","https://openalex.org/W2150981204"],"abstract_inverted_index":{"Constant":[0],"folding":[1,20],"reduces":[2],"area":[3],"and":[4,54],"enables":[5],"greater":[6],"parallelism,":[7],"but":[8],"requires":[9],"circuits":[10],"with":[11,29],"constant":[12,19],"inputs.":[13],"In":[14],"this":[15,71],"work,":[16],"we":[17,69],"extend":[18],"to":[21,75],"support":[22],"pseudo-constants,":[23],"which":[24,47],"are":[25],"values":[26,53],"that":[27],"change":[28],"low":[30],"frequency.":[31],"We":[32],"present":[33],"a":[34,76],"method":[35],"of":[36,45],"pseudo-constant":[37,52,61],"logic":[38,49,58],"optimization":[39,72],"based":[40],"on":[41,82],"dynamically":[42],"reconfigurable":[43],"capabilities":[44],"FPGAs,":[46],"optimizes":[48],"for":[50,66],"different":[51],"then":[55],"reconfigures":[56],"the":[57,60],"whenever":[59],"changes.":[62],"Although":[63],"not":[64],"beneficial":[65],"all":[67],"logic,":[68],"show":[70],"achieves":[73],"up":[74],"1.25x":[77],"increase":[78],"in":[79],"functional":[80],"density":[81],"Xilinx":[83],"Virtex":[84],"5":[85],"FPGAs.":[86]},"counts_by_year":[{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}