{"id":"https://openalex.org/W2149279796","doi":"https://doi.org/10.1109/asap.2010.5541015","title":"A forwarding-sensitive instruction scheduling approach to reduce register file constraints in VLIW architectures","display_name":"A forwarding-sensitive instruction scheduling approach to reduce register file constraints in VLIW architectures","publication_year":2010,"publication_date":"2010-07-01","ids":{"openalex":"https://openalex.org/W2149279796","doi":"https://doi.org/10.1109/asap.2010.5541015","mag":"2149279796"},"language":"en","primary_location":{"id":"doi:10.1109/asap.2010.5541015","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2010.5541015","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038123706","display_name":"Guillermo Pay\u00e1\u2013Vay\u00e1","orcid":"https://orcid.org/0000-0003-3503-8386"},"institutions":[{"id":"https://openalex.org/I114112103","display_name":"Leibniz University Hannover","ror":"https://ror.org/0304hq317","country_code":"DE","type":"education","lineage":["https://openalex.org/I114112103"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Guillermo Paya-Vaya","raw_affiliation_strings":["Institute of Microelectronic Systems, Leibniz Universit\u00e4t Hannover, Hannover, Germany"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic Systems, Leibniz Universit\u00e4t Hannover, Hannover, Germany","institution_ids":["https://openalex.org/I114112103"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038352122","display_name":"Javier Mart\u00edn-Langerwerf","orcid":null},"institutions":[{"id":"https://openalex.org/I114112103","display_name":"Leibniz University Hannover","ror":"https://ror.org/0304hq317","country_code":"DE","type":"education","lineage":["https://openalex.org/I114112103"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Javier Martin-Langerwerf","raw_affiliation_strings":["Institute of Microelectronic Systems, Leibniz Universit\u00e4t Hannover, Hannover, Germany"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic Systems, Leibniz Universit\u00e4t Hannover, Hannover, Germany","institution_ids":["https://openalex.org/I114112103"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016532646","display_name":"Holger Blume","orcid":"https://orcid.org/0000-0002-0640-6875"},"institutions":[{"id":"https://openalex.org/I114112103","display_name":"Leibniz University Hannover","ror":"https://ror.org/0304hq317","country_code":"DE","type":"education","lineage":["https://openalex.org/I114112103"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Holger Blume","raw_affiliation_strings":["Institute of Microelectronic Systems, Leibniz Universit\u00e4t Hannover, Hannover, Germany"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic Systems, Leibniz Universit\u00e4t Hannover, Hannover, Germany","institution_ids":["https://openalex.org/I114112103"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5050808949","display_name":"P. Pirsch","orcid":null},"institutions":[{"id":"https://openalex.org/I114112103","display_name":"Leibniz University Hannover","ror":"https://ror.org/0304hq317","country_code":"DE","type":"education","lineage":["https://openalex.org/I114112103"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Peter Pirsch","raw_affiliation_strings":["Institute of Microelectronic Systems, Leibniz Universit\u00e4t Hannover, Hannover, Germany"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic Systems, Leibniz Universit\u00e4t Hannover, Hannover, Germany","institution_ids":["https://openalex.org/I114112103"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5038123706"],"corresponding_institution_ids":["https://openalex.org/I114112103"],"apc_list":null,"apc_paid":null,"fwci":0.3371,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.60945403,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"151","last_page":"158"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11019","display_name":"Image Enhancement Techniques","score":0.9897000193595886,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8833867907524109},{"id":"https://openalex.org/keywords/very-long-instruction-word","display_name":"Very long instruction word","score":0.858386754989624},{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.7569835186004639},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5208954811096191},{"id":"https://openalex.org/keywords/instruction-scheduling","display_name":"Instruction scheduling","score":0.5078096985816956},{"id":"https://openalex.org/keywords/codec","display_name":"Codec","score":0.5020828247070312},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.44417837262153625},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.38017404079437256},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2651113271713257},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.22215235233306885},{"id":"https://openalex.org/keywords/dynamic-priority-scheduling","display_name":"Dynamic priority scheduling","score":0.15339750051498413},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.1350216567516327}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8833867907524109},{"id":"https://openalex.org/C170595534","wikidata":"https://www.wikidata.org/wiki/Q249743","display_name":"Very long instruction word","level":2,"score":0.858386754989624},{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.7569835186004639},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5208954811096191},{"id":"https://openalex.org/C73564150","wikidata":"https://www.wikidata.org/wiki/Q11417093","display_name":"Instruction scheduling","level":5,"score":0.5078096985816956},{"id":"https://openalex.org/C161765866","wikidata":"https://www.wikidata.org/wiki/Q184748","display_name":"Codec","level":2,"score":0.5020828247070312},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.44417837262153625},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.38017404079437256},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2651113271713257},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.22215235233306885},{"id":"https://openalex.org/C107568181","wikidata":"https://www.wikidata.org/wiki/Q5319000","display_name":"Dynamic priority scheduling","level":3,"score":0.15339750051498413},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.1350216567516327},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C119948110","wikidata":"https://www.wikidata.org/wiki/Q7858726","display_name":"Two-level scheduling","level":4,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asap.2010.5541015","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2010.5541015","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8700000047683716}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1555915743","https://openalex.org/W1589228771","https://openalex.org/W1980768932","https://openalex.org/W2007842093","https://openalex.org/W2016271465","https://openalex.org/W2062603907","https://openalex.org/W2110263160","https://openalex.org/W2119724710","https://openalex.org/W2121840029","https://openalex.org/W2122439715","https://openalex.org/W2131494297","https://openalex.org/W2143188883","https://openalex.org/W2148051985","https://openalex.org/W2153076498","https://openalex.org/W2158385898","https://openalex.org/W2163982432","https://openalex.org/W4244495268","https://openalex.org/W4302366751","https://openalex.org/W6633127185","https://openalex.org/W6682005402"],"related_works":["https://openalex.org/W89872709","https://openalex.org/W2581286023","https://openalex.org/W788524553","https://openalex.org/W2387572761","https://openalex.org/W2054117411","https://openalex.org/W2049097986","https://openalex.org/W2357256492","https://openalex.org/W3022819336","https://openalex.org/W2016285626","https://openalex.org/W4248406484"],"abstract_inverted_index":{"This":[0,34,66,135],"paper":[1],"presents":[2],"a":[3,71,131,155],"forwarding-based":[4],"approach":[5,35],"to":[6,46,115,120,139],"increase":[7],"the":[8,13,37,48,57,62,79,110,140,159],"code":[9,63,88],"compaction":[10,64],"and":[11,76,126],"consequently":[12],"processing":[14],"performance":[15,116,142],"of":[16,31,50,56,61,118,161],"VLIW":[17,44,133],"media-processors":[18],"that":[19,145],"implement":[20],"monolithic":[21],"or":[22],"partitioned":[23],"register":[24],"file":[25],"(RF)":[26],"organizations":[27],"with":[28,157],"reduced":[29],"number":[30,49,160],"read/write":[32],"ports.":[33,162],"exploits":[36],"forwarding":[38],"mechanism":[39],"implemented":[40],"in":[41,100,151],"common":[42,124],"pipelined":[43],"architectures":[45],"reduce":[47],"RF":[51,67,156],"accesses,":[52],"which":[53],"is":[54,98,136],"one":[55],"main":[58],"limiting":[59],"factors":[60],"process.":[65],"access":[68],"reduction":[69],"enables":[70],"higher":[72],"instruction":[73],"scheduling":[74,96,112],"efficiency":[75],"eventually":[77],"decreases":[78],"power":[80],"consumption,":[81],"without":[82],"requiring":[83],"extra":[84],"hardware.":[85],"A":[86],"forwarding-sensitive":[87],"generation":[89],"algorithm":[90,97,113],"based":[91],"on":[92,130],"an":[93],"enhanced":[94],"list":[95],"described":[99],"detail.":[101],"In":[102],"addition,":[103],"three":[104],"case":[105],"studies":[106],"are":[107],"presented,":[108],"where":[109],"proposed":[111],"leads":[114],"improvements":[117],"up":[119],"8.4%":[121],"when":[122,149],"running":[123],"image":[125],"video":[127],"codec":[128],"tasks":[129],"generic":[132],"architecture.":[134],"attractively":[137],"close":[138],"maximum":[141],"improvement":[143],"(11.4%)":[144],"can":[146],"be":[147],"achieved":[148],"investing":[150],"hardware":[152],"by":[153],"using":[154],"twice":[158]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
