{"id":"https://openalex.org/W2139092702","doi":"https://doi.org/10.1109/asap.2010.5540753","title":"Design of throughput-optimized arrays from recurrence abstractions","display_name":"Design of throughput-optimized arrays from recurrence abstractions","publication_year":2010,"publication_date":"2010-07-01","ids":{"openalex":"https://openalex.org/W2139092702","doi":"https://doi.org/10.1109/asap.2010.5540753","mag":"2139092702"},"language":"en","primary_location":{"id":"doi:10.1109/asap.2010.5540753","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2010.5540753","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5105839606","display_name":"Arpith C. Jacob","orcid":null},"institutions":[{"id":"https://openalex.org/I204465549","display_name":"Washington University in St. Louis","ror":"https://ror.org/01yc7t268","country_code":"US","type":"education","lineage":["https://openalex.org/I204465549"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Arpith C. Jacob","raw_affiliation_strings":["Department of Computer Science and Engineering, Washington University,  Saint Louis, USA","Dept. of Computer Science and Engineering, Washington University in St. Louis"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Washington University,  Saint Louis, USA","institution_ids":["https://openalex.org/I204465549"]},{"raw_affiliation_string":"Dept. of Computer Science and Engineering, Washington University in St. Louis","institution_ids":["https://openalex.org/I204465549"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080937008","display_name":"Jeremy Buhler","orcid":"https://orcid.org/0000-0002-4159-4226"},"institutions":[{"id":"https://openalex.org/I204465549","display_name":"Washington University in St. Louis","ror":"https://ror.org/01yc7t268","country_code":"US","type":"education","lineage":["https://openalex.org/I204465549"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jeremy D. Buhler","raw_affiliation_strings":["Department of Computer Science and Engineering, Washington University,  Saint Louis, USA","Dept. of Computer Science and Engineering, Washington University in St. Louis"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Washington University,  Saint Louis, USA","institution_ids":["https://openalex.org/I204465549"]},{"raw_affiliation_string":"Dept. of Computer Science and Engineering, Washington University in St. Louis","institution_ids":["https://openalex.org/I204465549"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5006814645","display_name":"Roger D. Chamberlain","orcid":"https://orcid.org/0000-0002-7207-6106"},"institutions":[{"id":"https://openalex.org/I204465549","display_name":"Washington University in St. Louis","ror":"https://ror.org/01yc7t268","country_code":"US","type":"education","lineage":["https://openalex.org/I204465549"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Roger D. Chamberlain","raw_affiliation_strings":["Department of Computer Science and Engineering, Washington University,  Saint Louis, USA","Dept. of Computer Science and Engineering, Washington University in St. Louis"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Washington University,  Saint Louis, USA","institution_ids":["https://openalex.org/I204465549"]},{"raw_affiliation_string":"Dept. of Computer Science and Engineering, Washington University in St. Louis","institution_ids":["https://openalex.org/I204465549"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5105839606"],"corresponding_institution_ids":["https://openalex.org/I204465549"],"apc_list":null,"apc_paid":null,"fwci":0.7581,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.7483955,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"133","last_page":"140"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9940000176429749,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9940000176429749,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9923999905586243,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10222","display_name":"Genomics and Chromatin Dynamics","score":0.991599977016449,"subfield":{"id":"https://openalex.org/subfields/1312","display_name":"Molecular Biology"},"field":{"id":"https://openalex.org/fields/13","display_name":"Biochemistry, Genetics and Molecular Biology"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7720097303390503},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6920183300971985},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.65630704164505},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.6558254361152649},{"id":"https://openalex.org/keywords/systolic-array","display_name":"Systolic array","score":0.6473380923271179},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6254467964172363},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6197702288627625},{"id":"https://openalex.org/keywords/vector-processor","display_name":"Vector processor","score":0.4351691007614136},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.4289016127586365},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.37807488441467285},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.26882559061050415},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.16135790944099426},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.1395479142665863}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7720097303390503},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6920183300971985},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.65630704164505},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.6558254361152649},{"id":"https://openalex.org/C150741067","wikidata":"https://www.wikidata.org/wiki/Q2377218","display_name":"Systolic array","level":3,"score":0.6473380923271179},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6254467964172363},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6197702288627625},{"id":"https://openalex.org/C161824985","wikidata":"https://www.wikidata.org/wiki/Q919509","display_name":"Vector processor","level":2,"score":0.4351691007614136},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.4289016127586365},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.37807488441467285},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.26882559061050415},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.16135790944099426},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.1395479142665863},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/asap.2010.5540753","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2010.5540753","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.395.8790","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.395.8790","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ccrc.wustl.edu/~roger/papers/jbc10b.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.4699999988079071}],"awards":[],"funders":[{"id":"https://openalex.org/F4320332161","display_name":"National Institutes of Health","ror":"https://ror.org/01cwqze88"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W296395453","https://openalex.org/W1530279678","https://openalex.org/W1596780177","https://openalex.org/W1968698000","https://openalex.org/W1970141743","https://openalex.org/W2033787819","https://openalex.org/W2054931730","https://openalex.org/W2097670944","https://openalex.org/W2137709353","https://openalex.org/W2146696273","https://openalex.org/W2147543317","https://openalex.org/W2148631003","https://openalex.org/W2157758640","https://openalex.org/W2162103705","https://openalex.org/W3143608323","https://openalex.org/W4230944386","https://openalex.org/W4232919122","https://openalex.org/W6610527614","https://openalex.org/W6635631693"],"related_works":["https://openalex.org/W2619340758","https://openalex.org/W1985549667","https://openalex.org/W3137340192","https://openalex.org/W2056543843","https://openalex.org/W2048874106","https://openalex.org/W833841031","https://openalex.org/W1566904673","https://openalex.org/W1995431248","https://openalex.org/W2514009251","https://openalex.org/W2114287756"],"abstract_inverted_index":{"Many":[0],"compute-bound":[1],"applications":[2,38],"have":[3,154],"seen":[4],"order-of-magnitude":[5],"speedups":[6],"using":[7],"special-purpose":[8],"accelerators.":[9],"FPGAs":[10],"in":[11,113,141,199],"particular":[12],"are":[13,212,224],"good":[14],"at":[15],"implementing":[16],"recurrence":[17,27],"equations":[18,28],"realized":[19],"as":[20],"arrays.":[21],"Existing":[22],"high-level":[23],"synthesis":[24],"approaches":[25],"for":[26,162,209],"produce":[29],"an":[30,92,107,123],"array":[31,84,108,124,168],"that":[32,39,119,206],"is":[33,57,97,125,145,169],"latency-space":[34,175],"optimal.":[35],"We":[36,117,153,185],"target":[37],"operate":[40],"on":[41,106],"a":[42,49,69,82,114,187,196,228],"large":[43],"collection":[44],"of":[45,51,62,81,91,122,130,134],"small":[46],"inputs,":[47],"e.g.":[48],"database":[50],"biological":[52],"sequences,":[53],"where":[54],"overall":[55],"throughput":[56,80,121,210],"the":[58,75,120,128,131,142,149,173,216],"most":[59],"important":[60],"measure":[61],"performance.":[63],"In":[64],"this":[65,156],"work,":[66],"we":[67],"introduce":[68],"new":[70],"design-space":[71],"exploration":[72],"procedure":[73],"within":[74],"polyhedral":[76],"framework":[77],"to":[78,86,98,158],"optimize":[79],"systolic":[83],"subject":[85],"area":[87,208],"and":[88,109,211],"bandwidth":[89],"constraints":[90],"FPGA":[93],"device.":[94],"Our":[95,166,201],"approach":[96],"exploit":[99],"additional":[100,204],"parallelism":[101],"by":[102,127,138,148,191],"pipelining":[103],"multiple":[104,110],"inputs":[105],"iteration":[111,135],"vectors":[112,136],"processing":[115],"element.":[116],"prove":[118],"given":[126],"inverse":[129],"maximum":[132],"number":[133],"executed":[137],"any":[139],"processor":[140,192],"array,":[143,177],"which":[144],"determined":[146],"solely":[147],"array's":[150],"projection":[151],"vector.":[152],"applied":[155],"observation":[157],"discover":[159],"novel":[160,222],"arrays":[161,205,223],"Nussinov":[163],"RNA":[164],"folding.":[165],"throughput-optimized":[167],"2\u00d7":[170,189],"faster":[171,214,226],"than":[172,215,227],"standard":[174],"optimal":[176],"yet":[178],"it":[179],"uses":[180],"15%":[181],"fewer":[182],"LUT":[183],"resources.":[184,200],"achieve":[186],"further":[188],"speedup":[190],"pipelining,":[193],"with":[194],"only":[195],"37%":[197],"increase":[198],"tool":[202],"suggests":[203],"trade":[207],"4-5\u00d7":[213],"currently":[217],"used":[218],"latency-optimized":[219],"array.":[220],"These":[221],"70-172\u00d7":[225],"software":[229],"baseline.":[230]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
