{"id":"https://openalex.org/W2126308165","doi":"https://doi.org/10.1109/asap.2008.4580188","title":"Loop-oriented metrics for exploring an application-specific architecture design-space","display_name":"Loop-oriented metrics for exploring an application-specific architecture design-space","publication_year":2008,"publication_date":"2008-07-01","ids":{"openalex":"https://openalex.org/W2126308165","doi":"https://doi.org/10.1109/asap.2008.4580188","mag":"2126308165"},"language":"en","primary_location":{"id":"doi:10.1109/asap.2008.4580188","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2008.4580188","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Application-Specific Systems, Architectures and Processors","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110225451","display_name":"Maria Mbaye","orcid":null},"institutions":[{"id":"https://openalex.org/I29607241","display_name":"\u00c9cole Normale Sup\u00e9rieure - PSL","ror":"https://ror.org/05a0dhs15","country_code":"FR","type":"other","lineage":["https://openalex.org/I2746051580","https://openalex.org/I29607241"]},{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA","FR"],"is_corresponding":true,"raw_author_name":"Maria Mbaye","raw_affiliation_strings":["Department of Electrical Engineering, \u00c9cole Polytechnique de Montr\u00e9al, Montreal, QUE, Canada","Dept. of Electr. Eng., Ecole Polytech de Montreal, Montreal, QC"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, \u00c9cole Polytechnique de Montr\u00e9al, Montreal, QUE, Canada","institution_ids":["https://openalex.org/I45683168"]},{"raw_affiliation_string":"Dept. of Electr. Eng., Ecole Polytech de Montreal, Montreal, QC","institution_ids":["https://openalex.org/I29607241","https://openalex.org/I45683168"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065902799","display_name":"Normand B\u00e9langer","orcid":null},"institutions":[{"id":"https://openalex.org/I29607241","display_name":"\u00c9cole Normale Sup\u00e9rieure - PSL","ror":"https://ror.org/05a0dhs15","country_code":"FR","type":"other","lineage":["https://openalex.org/I2746051580","https://openalex.org/I29607241"]},{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA","FR"],"is_corresponding":false,"raw_author_name":"Normand Belanger","raw_affiliation_strings":["Department of Electrical Engineering, \u00c9cole Polytechnique de Montr\u00e9al, Montreal, QUE, Canada","Dept. of Electr. Eng., Ecole Polytech de Montreal, Montreal, QC"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, \u00c9cole Polytechnique de Montr\u00e9al, Montreal, QUE, Canada","institution_ids":["https://openalex.org/I45683168"]},{"raw_affiliation_string":"Dept. of Electr. Eng., Ecole Polytech de Montreal, Montreal, QC","institution_ids":["https://openalex.org/I29607241","https://openalex.org/I45683168"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038488044","display_name":"Yvon Savaria","orcid":"https://orcid.org/0000-0002-3404-9959"},"institutions":[{"id":"https://openalex.org/I29607241","display_name":"\u00c9cole Normale Sup\u00e9rieure - PSL","ror":"https://ror.org/05a0dhs15","country_code":"FR","type":"other","lineage":["https://openalex.org/I2746051580","https://openalex.org/I29607241"]},{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA","FR"],"is_corresponding":false,"raw_author_name":"Yvon Savaria","raw_affiliation_strings":["Department of Electrical Engineering, \u00c9cole Polytechnique de Montr\u00e9al, Montreal, QUE, Canada","Dept. of Electr. Eng., Ecole Polytech de Montreal, Montreal, QC"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, \u00c9cole Polytechnique de Montr\u00e9al, Montreal, QUE, Canada","institution_ids":["https://openalex.org/I45683168"]},{"raw_affiliation_string":"Dept. of Electr. Eng., Ecole Polytech de Montreal, Montreal, QC","institution_ids":["https://openalex.org/I29607241","https://openalex.org/I45683168"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074743707","display_name":"Samuel Pierre","orcid":"https://orcid.org/0000-0001-8063-8773"},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Samuel Pierre","raw_affiliation_strings":["Department of Computer Engineering, \u00c9cole Polytechnique de Montr\u00e9al, Montreal, QUE, Canada","Dept. of Computer Engineering, \u00c9cole Polytechnique de Montr\u00e9al, P.O. Box 6079 Station Centre-Ville, QC, H3C 3A7, Canada#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, \u00c9cole Polytechnique de Montr\u00e9al, Montreal, QUE, Canada","institution_ids":["https://openalex.org/I45683168"]},{"raw_affiliation_string":"Dept. of Computer Engineering, \u00c9cole Polytechnique de Montr\u00e9al, P.O. Box 6079 Station Centre-Ville, QC, H3C 3A7, Canada#TAB#","institution_ids":["https://openalex.org/I45683168"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5110225451"],"corresponding_institution_ids":["https://openalex.org/I29607241","https://openalex.org/I45683168"],"apc_list":null,"apc_paid":null,"fwci":0.3454,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.70038528,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"1","issue":null,"first_page":"257","last_page":"262"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.834811806678772},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.7246240973472595},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5855571627616882},{"id":"https://openalex.org/keywords/reuse","display_name":"Reuse","score":0.5741625428199768},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5588964819908142},{"id":"https://openalex.org/keywords/acceleration","display_name":"Acceleration","score":0.46630942821502686},{"id":"https://openalex.org/keywords/loop-tiling","display_name":"Loop tiling","score":0.45929330587387085},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4335471987724304},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.41120994091033936},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3605794310569763},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.35010796785354614},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.32822996377944946},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3216075301170349},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2859657108783722},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.1428709328174591}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.834811806678772},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.7246240973472595},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5855571627616882},{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.5741625428199768},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5588964819908142},{"id":"https://openalex.org/C117896860","wikidata":"https://www.wikidata.org/wiki/Q11376","display_name":"Acceleration","level":2,"score":0.46630942821502686},{"id":"https://openalex.org/C11799548","wikidata":"https://www.wikidata.org/wiki/Q6675847","display_name":"Loop tiling","level":3,"score":0.45929330587387085},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4335471987724304},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.41120994091033936},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3605794310569763},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.35010796785354614},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.32822996377944946},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3216075301170349},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2859657108783722},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.1428709328174591},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C74650414","wikidata":"https://www.wikidata.org/wiki/Q11397","display_name":"Classical mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/asap.2008.4580188","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2008.4580188","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Application-Specific Systems, Architectures and Processors","raw_type":"proceedings-article"},{"id":"pmh:oai:publications.polymtl.ca:20470","is_oa":false,"landing_page_url":"https://publications.polymtl.ca/20470/","pdf_url":null,"source":{"id":"https://openalex.org/S4306401013","display_name":"PolyPublie (\u00c9cole Polytechnique de Montr\u00e9al)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I45683168","host_organization_name":"Polytechnique Montr\u00e9al","host_organization_lineage":["https://openalex.org/I45683168"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Communication de conf\u00e9rence"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320334593","display_name":"Natural Sciences and Engineering Research Council of Canada","ror":"https://ror.org/01h531d29"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1555915743","https://openalex.org/W1558000309","https://openalex.org/W1577039630","https://openalex.org/W1994115836","https://openalex.org/W2000095678","https://openalex.org/W2011078763","https://openalex.org/W2032391783","https://openalex.org/W2103618033","https://openalex.org/W2131442634","https://openalex.org/W2140928152","https://openalex.org/W2165187428","https://openalex.org/W2165892109","https://openalex.org/W4239726226"],"related_works":["https://openalex.org/W2168940796","https://openalex.org/W4282568311","https://openalex.org/W4313484792","https://openalex.org/W2951473296","https://openalex.org/W2883928845","https://openalex.org/W4288420200","https://openalex.org/W3145095675","https://openalex.org/W2024329643","https://openalex.org/W4365793791","https://openalex.org/W3134072570"],"abstract_inverted_index":{"Since":[0],"ASIPs":[1,24],"were":[2],"introduced":[3],"in":[4],"the":[5,48,82,99,105,112,116],"HW/SW":[6],"architecture":[7],"design":[8],"space,":[9],"application":[10],"partitioning":[11,49],"has":[12],"become":[13],"more":[14,18,72],"complex.":[15],"Designers":[16],"have":[17],"ways":[19],"to":[20],"accelerate":[21],"applications:":[22],"with":[23,29],"of":[25,51,61,107,115],"various":[26],"kinds":[27],"or":[28],"dedicated":[30],"hardware":[31],"modules.":[32],"In":[33],"this":[34],"paper,":[35],"we":[36],"present":[37],"loop-oriented":[38],"metrics":[39,55],"that":[40,80],"will":[41],"be":[42],"used":[43],"during":[44],"design-space":[45],"exploration":[46],"for":[47,98],"process":[50],"C-based":[52],"designs.":[53],"These":[54],"help":[56],"designers":[57],"determine":[58,88],"which":[59,89],"aspect":[60],"loop":[62],"iterations,":[63],"between":[64],"data":[65,94],"memory":[66],"accesses":[67],"and":[68],"ALU/Control":[69],"operations,":[70],"offers":[71],"acceleration":[73,113],"potential.":[74],"We":[75,103],"implemented":[76],"a":[77,119],"profiler-scheduler":[78],"LOOPPROF":[79],"gathers":[81],"metrics.":[83],"Our":[84],"tool":[85,109],"also":[86],"helps":[87],"optimization":[90],"techniques":[91],"such":[92],"as":[93],"reuse":[95],"are":[96],"suitable":[97],"considered":[100],"code":[101],"segments.":[102],"demonstrate":[104],"use":[106],"our":[108],"by":[110],"exploring":[111],"possibilities":[114],"ELA":[117],"Deinterlacer,":[118],"video":[120],"processing":[121],"algorithm.":[122]},"counts_by_year":[],"updated_date":"2026-04-25T08:17:42.794288","created_date":"2025-10-10T00:00:00"}