{"id":"https://openalex.org/W2164764563","doi":"https://doi.org/10.1109/asap.2008.4580152","title":"Fully-pipelined efficient architectures for FPGA realization of discrete Hadamard transform","display_name":"Fully-pipelined efficient architectures for FPGA realization of discrete Hadamard transform","publication_year":2008,"publication_date":"2008-07-01","ids":{"openalex":"https://openalex.org/W2164764563","doi":"https://doi.org/10.1109/asap.2008.4580152","mag":"2164764563"},"language":"en","primary_location":{"id":"doi:10.1109/asap.2008.4580152","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2008.4580152","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Application-Specific Systems, Architectures and Processors","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025809855","display_name":"Pramod Kumar Meher","orcid":"https://orcid.org/0000-0003-0992-1159"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":true,"raw_author_name":"P. K. Meher","raw_affiliation_strings":["School of Computer Engineering, Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"School of Computer Engineering, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5049913930","display_name":"Jagdish C. Patra","orcid":"https://orcid.org/0000-0002-6257-0469"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"J. C. Patra","raw_affiliation_strings":["School of Computer Engineering, Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"School of Computer Engineering, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5025809855"],"corresponding_institution_ids":["https://openalex.org/I172675005"],"apc_list":null,"apc_paid":null,"fwci":1.1198,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.80160947,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"2","issue":null,"first_page":"43","last_page":"48"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.994700014591217,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.994700014591217,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9811000227928162,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10767","display_name":"Advanced Photonic Communication Systems","score":0.9778000116348267,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.7497985363006592},{"id":"https://openalex.org/keywords/hadamard-transform","display_name":"Hadamard transform","score":0.7115360498428345},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6791647672653198},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6570699214935303},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.5588403344154358},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.5487256646156311},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.49280741810798645},{"id":"https://openalex.org/keywords/kernel","display_name":"Kernel (algebra)","score":0.46477821469306946},{"id":"https://openalex.org/keywords/discrete-hartley-transform","display_name":"Discrete Hartley transform","score":0.44791045784950256},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.41212159395217896},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3539361357688904},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32286536693573},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.20828554034233093},{"id":"https://openalex.org/keywords/fourier-transform","display_name":"Fourier transform","score":0.1463927924633026},{"id":"https://openalex.org/keywords/fractional-fourier-transform","display_name":"Fractional Fourier transform","score":0.14561641216278076},{"id":"https://openalex.org/keywords/discrete-mathematics","display_name":"Discrete mathematics","score":0.10268720984458923}],"concepts":[{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.7497985363006592},{"id":"https://openalex.org/C60292330","wikidata":"https://www.wikidata.org/wiki/Q1014065","display_name":"Hadamard transform","level":2,"score":0.7115360498428345},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6791647672653198},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6570699214935303},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.5588403344154358},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.5487256646156311},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.49280741810798645},{"id":"https://openalex.org/C74193536","wikidata":"https://www.wikidata.org/wiki/Q574844","display_name":"Kernel (algebra)","level":2,"score":0.46477821469306946},{"id":"https://openalex.org/C192853989","wikidata":"https://www.wikidata.org/wiki/Q1006531","display_name":"Discrete Hartley transform","level":5,"score":0.44791045784950256},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.41212159395217896},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3539361357688904},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32286536693573},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.20828554034233093},{"id":"https://openalex.org/C102519508","wikidata":"https://www.wikidata.org/wiki/Q6520159","display_name":"Fourier transform","level":2,"score":0.1463927924633026},{"id":"https://openalex.org/C76563020","wikidata":"https://www.wikidata.org/wiki/Q4817582","display_name":"Fractional Fourier transform","level":4,"score":0.14561641216278076},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.10268720984458923},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C203024314","wikidata":"https://www.wikidata.org/wiki/Q1365258","display_name":"Fourier analysis","level":3,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/asap.2008.4580152","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2008.4580152","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Application-Specific Systems, Architectures and Processors","raw_type":"proceedings-article"},{"id":"pmh:oai:researchbank.swinburne.edu.au:bbc40aa1-8422-46c2-b22c-3e28c7647c93/1","is_oa":false,"landing_page_url":"http://hdl.handle.net/1959.3/385199","pdf_url":null,"source":{"id":"https://openalex.org/S4306401157","display_name":"Swinburne Research Bank (Swinburne University of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I57093077","host_organization_name":"Swinburne University of Technology","host_organization_lineage":["https://openalex.org/I57093077"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2008), Leuven, Belgium, 2-4 July 2008, pp. 43-48","raw_type":""}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1485093184","https://openalex.org/W1606480398","https://openalex.org/W2003500107","https://openalex.org/W2012806307","https://openalex.org/W2018982470","https://openalex.org/W2039544376","https://openalex.org/W2065465262","https://openalex.org/W2066306414","https://openalex.org/W2080398304","https://openalex.org/W2104002218","https://openalex.org/W2117698856","https://openalex.org/W2129599986","https://openalex.org/W2148240122","https://openalex.org/W4247712687","https://openalex.org/W6628878919","https://openalex.org/W6636396655"],"related_works":["https://openalex.org/W3004362061","https://openalex.org/W4297665406","https://openalex.org/W2364622490","https://openalex.org/W2042515040","https://openalex.org/W2383986884","https://openalex.org/W2356141508","https://openalex.org/W4379386706","https://openalex.org/W2544043553","https://openalex.org/W1735031787","https://openalex.org/W2390807153"],"abstract_inverted_index":{"Fully-pipelined":[0],"simple":[1],"modular":[2,30],"structures":[3],"are":[4,107],"presented":[5],"in":[6,109,126],"this":[7],"paper":[8],"for":[9,32,116,163],"efficient":[10],"hardware":[11],"realization":[12],"of":[13,22,45,62,92,151,166],"discrete":[14],"Hadamard":[15],"transform":[16,33],"(HT).":[17],"From":[18,136],"the":[19,43,60,137,144,160],"kernel":[20],"matrix":[21],"HT,":[23],"we":[24],"have":[25],"derived":[26],"four":[27,69],"different":[28,127],"pipelined":[29],"designs":[31,146],"length":[34],"N":[35,47,99],"=":[36,48,98],"4.":[37],"It":[38],"is":[39,141],"shown":[40],"further":[41],"that":[42,143],"HT":[44,56,61,71],"transform-length":[46,63],"8":[49],"can":[50,65,86],"be":[51,66,77,87,124],"obtained":[52,67],"from":[53,68,79,89],"two":[54],"4-point":[55,70],"modules,":[57],"and":[58,118,120,134,153],"similarly,":[59],"N=16":[64],"modules.":[72],"Long-length":[73],"transforms":[74,85],"may,":[75],"however,":[76],"computed":[78,88],"these":[80],"short-length":[81],"modules":[82],"as":[83],"N-point":[84],"2M":[90],"number":[91,150],"M":[93,97],"point":[94],"HT-modules,":[95],"where":[96],"<sup":[100],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[101],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">1/2</sup>":[102],".":[103],"The":[104],"proposed":[105,145],"architectures":[106,162],"coded":[108],"VHDL,":[110],"simulated":[111],"by":[112],"Xilinx":[113],"ISE":[114],"tool":[115],"validation":[117],"testing;":[119],"synthesized":[121],"thereafter":[122],"to":[123],"implemented":[125],"FPGA":[128,164],"devices,":[129],"e.g.,":[130],"Virtex-E,":[131],"Virtex-II":[132],"Pro":[133],"Virtex-4.":[135],"synthesis":[138],"result,":[139],"it":[140],"found":[142],"involve":[147],"considerably":[148],"less":[149],"slices":[152],"provide":[154],"significantly":[155],"higher":[156],"best-achievable-frequency":[157],"compared":[158],"with":[159],"existing":[161],"implementation":[165],"HT.":[167]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":4},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}