{"id":"https://openalex.org/W2120024496","doi":"https://doi.org/10.1109/asap.2007.4429959","title":"Mapping and Topology Customization Approaches for Application-Specific STNoC Designs","display_name":"Mapping and Topology Customization Approaches for Application-Specific STNoC Designs","publication_year":2007,"publication_date":"2007-07-01","ids":{"openalex":"https://openalex.org/W2120024496","doi":"https://doi.org/10.1109/asap.2007.4429959","mag":"2120024496"},"language":"en","primary_location":{"id":"doi:10.1109/asap.2007.4429959","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2007.4429959","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5077005193","display_name":"Gianluca Palermo","orcid":"https://orcid.org/0000-0001-7955-8012"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Gianluca Palermo","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy","Politecnico di Milano , Milano"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy","institution_ids":["https://openalex.org/I93860229"]},{"raw_affiliation_string":"Politecnico di Milano , Milano","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041843364","display_name":"Giovanni Mariani","orcid":null},"institutions":[{"id":"https://openalex.org/I57201433","display_name":"Universit\u00e0 della Svizzera italiana","ror":"https://ror.org/03c4atk17","country_code":"CH","type":"education","lineage":["https://openalex.org/I57201433"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Giovanni Mariani","raw_affiliation_strings":["ALaRI-Faculty of informatics, University of Lugano, Switzerland","ALaRI - Faculty of informatics - University of Lugano, giovanni.mariani@lu.unisi.ch"],"affiliations":[{"raw_affiliation_string":"ALaRI-Faculty of informatics, University of Lugano, Switzerland","institution_ids":["https://openalex.org/I57201433"]},{"raw_affiliation_string":"ALaRI - Faculty of informatics - University of Lugano, giovanni.mariani@lu.unisi.ch","institution_ids":["https://openalex.org/I57201433"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031461662","display_name":"Cristina Silvano","orcid":"https://orcid.org/0000-0003-1668-0883"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Cristina Silvano","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy","Politecnico di Milano - Dipartimento di Elettronica e Informazione, silvano@elet.polimi.it"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy","institution_ids":["https://openalex.org/I93860229"]},{"raw_affiliation_string":"Politecnico di Milano - Dipartimento di Elettronica e Informazione, silvano@elet.polimi.it","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050816276","display_name":"Riccardo Locatelli","orcid":null},"institutions":[{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]},{"id":"https://openalex.org/I131827901","display_name":"STMicroelectronics (Switzerland)","ror":"https://ror.org/00wm3b005","country_code":"CH","type":"company","lineage":["https://openalex.org/I131827901"]}],"countries":["CH","IT"],"is_corresponding":false,"raw_author_name":"Riccardo Locatelli","raw_affiliation_strings":["Advanced System Technology, STMicroelectronics, Italy","STMicroelectronics - Advanced System Technology, riccardo.locatelli@st.com"],"affiliations":[{"raw_affiliation_string":"Advanced System Technology, STMicroelectronics, Italy","institution_ids":["https://openalex.org/I4210154781"]},{"raw_affiliation_string":"STMicroelectronics - Advanced System Technology, riccardo.locatelli@st.com","institution_ids":["https://openalex.org/I131827901"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5009787535","display_name":"Marcello Coppola","orcid":"https://orcid.org/0000-0003-0414-9411"},"institutions":[{"id":"https://openalex.org/I131827901","display_name":"STMicroelectronics (Switzerland)","ror":"https://ror.org/00wm3b005","country_code":"CH","type":"company","lineage":["https://openalex.org/I131827901"]},{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["CH","IT"],"is_corresponding":false,"raw_author_name":"Marcello Coppola","raw_affiliation_strings":["Advanced System Technology, STMicroelectronics, Italy","STMicroelectronics - Advanced System Technology, marcello.coppola@st.com"],"affiliations":[{"raw_affiliation_string":"Advanced System Technology, STMicroelectronics, Italy","institution_ids":["https://openalex.org/I4210154781"]},{"raw_affiliation_string":"STMicroelectronics - Advanced System Technology, marcello.coppola@st.com","institution_ids":["https://openalex.org/I131827901"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5077005193"],"corresponding_institution_ids":["https://openalex.org/I93860229"],"apc_list":null,"apc_paid":null,"fwci":0.3209,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.66145971,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"1","issue":null,"first_page":"61","last_page":"68"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9937000274658203,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.8573904037475586},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7120615243911743},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.5161915421485901},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.4999351501464844},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.49639278650283813},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.4832073450088501},{"id":"https://openalex.org/keywords/personalization","display_name":"Personalization","score":0.4388201832771301},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.43177205324172974},{"id":"https://openalex.org/keywords/orthogonalization","display_name":"Orthogonalization","score":0.431654155254364},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.35606852173805237},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33809953927993774},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.27341675758361816},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17037692666053772},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.0985034704208374}],"concepts":[{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.8573904037475586},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7120615243911743},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.5161915421485901},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.4999351501464844},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.49639278650283813},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.4832073450088501},{"id":"https://openalex.org/C183003079","wikidata":"https://www.wikidata.org/wiki/Q1000371","display_name":"Personalization","level":2,"score":0.4388201832771301},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.43177205324172974},{"id":"https://openalex.org/C47559304","wikidata":"https://www.wikidata.org/wiki/Q1702189","display_name":"Orthogonalization","level":2,"score":0.431654155254364},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35606852173805237},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33809953927993774},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.27341675758361816},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17037692666053772},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0985034704208374},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C136764020","wikidata":"https://www.wikidata.org/wiki/Q466","display_name":"World Wide Web","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/asap.2007.4429959","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2007.4429959","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP)","raw_type":"proceedings-article"},{"id":"pmh:oai:re.public.polimi.it:11311/243945","is_oa":false,"landing_page_url":"http://hdl.handle.net/11311/243945","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":34,"referenced_works":["https://openalex.org/W1501077214","https://openalex.org/W1540027087","https://openalex.org/W1582835330","https://openalex.org/W1939228150","https://openalex.org/W2035296141","https://openalex.org/W2054302810","https://openalex.org/W2061779556","https://openalex.org/W2074890988","https://openalex.org/W2098156582","https://openalex.org/W2103714710","https://openalex.org/W2113615756","https://openalex.org/W2118961575","https://openalex.org/W2123184444","https://openalex.org/W2126349935","https://openalex.org/W2130610076","https://openalex.org/W2151174323","https://openalex.org/W2152150905","https://openalex.org/W2160642395","https://openalex.org/W2160847478","https://openalex.org/W2164703619","https://openalex.org/W2171950980","https://openalex.org/W2540500304","https://openalex.org/W2548514518","https://openalex.org/W2996989811","https://openalex.org/W3004157836","https://openalex.org/W3143713518","https://openalex.org/W3169463464","https://openalex.org/W4253408813","https://openalex.org/W6630005587","https://openalex.org/W6632077414","https://openalex.org/W6634901851","https://openalex.org/W6640384967","https://openalex.org/W6666114916","https://openalex.org/W6678764217"],"related_works":["https://openalex.org/W1980085932","https://openalex.org/W2594964164","https://openalex.org/W2030249421","https://openalex.org/W1966736993","https://openalex.org/W2022199660","https://openalex.org/W2547794540","https://openalex.org/W2161995522","https://openalex.org/W2102097772","https://openalex.org/W2102965264","https://openalex.org/W3207646743"],"abstract_inverted_index":{"Application-specific":[0],"network-oriented":[1],"communication":[2],"architectures":[3,19],"have":[4],"recently":[5],"become":[6],"an":[7],"effective":[8],"solution":[9],"to":[10,26,45,75,95,114],"support":[11,46],"high":[12],"bandwidth":[13],"Systems":[14],"on-Chip.":[15],"The":[16,83],"Network":[17,78],"on-Chip":[18,79],"considered":[20],"so":[21],"far":[22],"range":[23],"from":[24,88],"regular":[25],"fully":[27],"customized":[28],"topologies":[29,98],"for":[30],"application-specific":[31],"designs":[32],"requiring":[33],"high-level":[34],"bandwidth.":[35],"To":[36],"this":[37],"end,":[38],"a":[39],"network-centric":[40],"design":[41,48,56],"flow":[42],"is":[43],"necessary":[44],"the":[47,66,77,89,92,110,116],"space":[49],"exploration":[50],"of":[51,68,91,105,112,119],"complex":[52],"SoCs":[53],"with":[54,102],"tight":[55],"constraints.":[57],"This":[58],"paper":[59],"introduces":[60],"four":[61,84],"different":[62],"approaches":[63],"based":[64,108],"on":[65,109],"orthogonalization":[67],"core":[69],"mapping":[70],"and":[71,100],"topology":[72,106],"customization":[73,107],"applied":[74],"STNoC,":[76],"developed":[80],"by":[81],"STMicroelecronics.":[82],"methods":[85],"are":[86],"derived":[87],"combination":[90],"initial":[93],"mappings":[94],"two":[96,103],"standard":[97,120],"(ring":[99],"spidergon)":[101],"types":[104],"insertion":[111],"cross-links":[113],"reduce":[115],"network":[117],"distance":[118],"topologies.":[121]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2016-06-24T00:00:00"}
