{"id":"https://openalex.org/W2168092720","doi":"https://doi.org/10.1109/asap.2007.4429953","title":"A Self-Reconfigurable Implementation of the JPEG Encoder","display_name":"A Self-Reconfigurable Implementation of the JPEG Encoder","publication_year":2007,"publication_date":"2007-07-01","ids":{"openalex":"https://openalex.org/W2168092720","doi":"https://doi.org/10.1109/asap.2007.4429953","mag":"2168092720"},"language":"en","primary_location":{"id":"doi:10.1109/asap.2007.4429953","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2007.4429953","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041853964","display_name":"Antonino Tumeo","orcid":"https://orcid.org/0000-0001-9452-120X"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Antonino Tumeo","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038294114","display_name":"Matteo Monchiero","orcid":null},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Matteo Monchiero","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077005193","display_name":"Gianluca Palermo","orcid":"https://orcid.org/0000-0001-7955-8012"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Gianluca Palermo","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028565685","display_name":"Fabrizio Ferrandi","orcid":"https://orcid.org/0000-0003-0301-4419"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Fabrizio Ferrandi","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5014181688","display_name":"Donatella Sciuto","orcid":"https://orcid.org/0000-0001-9030-6940"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Donatella Sciuto","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5041853964"],"corresponding_institution_ids":["https://openalex.org/I93860229"],"apc_list":null,"apc_paid":null,"fwci":1.5833,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.84869271,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"24","last_page":"29"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8205239772796631},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.8126027584075928},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7418670654296875},{"id":"https://openalex.org/keywords/encoder","display_name":"Encoder","score":0.7275650501251221},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6925278306007385},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6821528673171997},{"id":"https://openalex.org/keywords/jpeg","display_name":"JPEG","score":0.5261313915252686},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.48644566535949707},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4845978021621704},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4589022994041443},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.4540775716304779},{"id":"https://openalex.org/keywords/data-compression","display_name":"Data compression","score":0.2523317039012909},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.10288071632385254}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8205239772796631},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.8126027584075928},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7418670654296875},{"id":"https://openalex.org/C118505674","wikidata":"https://www.wikidata.org/wiki/Q42586063","display_name":"Encoder","level":2,"score":0.7275650501251221},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6925278306007385},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6821528673171997},{"id":"https://openalex.org/C198751489","wikidata":"https://www.wikidata.org/wiki/Q2195","display_name":"JPEG","level":3,"score":0.5261313915252686},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.48644566535949707},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4845978021621704},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4589022994041443},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.4540775716304779},{"id":"https://openalex.org/C78548338","wikidata":"https://www.wikidata.org/wiki/Q2493","display_name":"Data compression","level":2,"score":0.2523317039012909},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.10288071632385254},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/asap.2007.4429953","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2007.4429953","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP)","raw_type":"proceedings-article"},{"id":"pmh:oai:re.public.polimi.it:11311/253815","is_oa":false,"landing_page_url":"http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4429953","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W117943111","https://openalex.org/W1491898100","https://openalex.org/W1535397071","https://openalex.org/W2022060843","https://openalex.org/W2066902831","https://openalex.org/W2089583925","https://openalex.org/W2098129944","https://openalex.org/W2099248913","https://openalex.org/W2104839467","https://openalex.org/W2109005188","https://openalex.org/W2115294662","https://openalex.org/W2123571123","https://openalex.org/W2124354872","https://openalex.org/W2124422907","https://openalex.org/W2127968420","https://openalex.org/W2130193491","https://openalex.org/W2135442895","https://openalex.org/W2137672309","https://openalex.org/W2139886987","https://openalex.org/W2142490124","https://openalex.org/W2145879814","https://openalex.org/W2146188244","https://openalex.org/W2161577181","https://openalex.org/W2163630291","https://openalex.org/W2163962121","https://openalex.org/W2584840801","https://openalex.org/W6672983240"],"related_works":["https://openalex.org/W2204754129","https://openalex.org/W4322751528","https://openalex.org/W2759209791","https://openalex.org/W2340647897","https://openalex.org/W2034458695","https://openalex.org/W1569711686","https://openalex.org/W1541284233","https://openalex.org/W2129154773","https://openalex.org/W2808484818","https://openalex.org/W1574948540"],"abstract_inverted_index":{"Dynamic":[0],"reconfiguration":[1],"allows":[2,76],"to":[3,13,50,64,109],"selectively":[4],"substitute":[5],"blocks":[6],"of":[7,18,27,45,69],"logic":[8],"at":[9],"run-time":[10],"in":[11],"order":[12],"improve":[14],"the":[15,25,46,59,92],"area":[16,79,98],"efficiency":[17],"a":[19,28,37,66,86,110],"FPGA":[20],"design.":[21],"This":[22],"paper":[23],"presents":[24],"design":[26],"JPEG":[29,94],"Encoder":[30],"which":[31,89,112],"exploits":[32],"this":[33,74],"feature.":[34],"We":[35,84],"propose":[36],"mixed":[38],"HW/SW":[39],"architecture,":[40],"where":[41],"most":[42],"compute-intensive":[43],"components":[44],"application":[47,68],"are":[48],"mapped":[49,115],"application-specific":[51],"HW":[52,116],"cores.":[53,117],"These":[54],"cores":[55],"dynamically":[56],"alternate":[57],"on":[58],"FPGA.":[60],"Our":[61],"purpose":[62],"is":[63],"describe":[65],"real-world":[67],"reconfigurable":[70,93],"computing,":[71],"illustrating":[72],"how":[73],"approach":[75],"for":[77],"saving":[78],"with":[80,107],"negligible":[81,104],"performance":[82,101],"overhead.":[83],"built":[85],"fully-working":[87],"prototype,":[88],"demonstrates":[90],"that":[91],"encoder":[95],"achieves":[96],"29.6%":[97],"saving,":[99],"1.5%":[100],"loss,":[102],"and":[103],"power":[105],"overhead":[106],"respect":[108],"solution":[111],"uses":[113],"statically":[114]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2016-06-24T00:00:00"}
