{"id":"https://openalex.org/W2135915979","doi":"https://doi.org/10.1109/asap.2003.1212828","title":"Hardware synthesis for multi-dimensional time","display_name":"Hardware synthesis for multi-dimensional time","publication_year":2004,"publication_date":"2004-03-01","ids":{"openalex":"https://openalex.org/W2135915979","doi":"https://doi.org/10.1109/asap.2003.1212828","mag":"2135915979"},"language":"en","primary_location":{"id":"doi:10.1109/asap.2003.1212828","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2003.1212828","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5046599885","display_name":"A.-C. Guillou","orcid":null},"institutions":[{"id":"https://openalex.org/I2802519937","display_name":"Institut de Recherche en Informatique et Syst\u00e8mes Al\u00e9atoires","ror":"https://ror.org/00myn0z94","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I205703379","https://openalex.org/I2802204017","https://openalex.org/I2802519937","https://openalex.org/I28221208","https://openalex.org/I4210127572","https://openalex.org/I4210159245","https://openalex.org/I56067802"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"A.-C. Guillou","raw_affiliation_strings":["Campus de Beaulieu, IRISA, Rennes, France","IRISA, Rennes, France"],"affiliations":[{"raw_affiliation_string":"Campus de Beaulieu, IRISA, Rennes, France","institution_ids":["https://openalex.org/I2802519937"]},{"raw_affiliation_string":"IRISA, Rennes, France","institution_ids":["https://openalex.org/I2802519937"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111996414","display_name":"Patrice Quinton","orcid":null},"institutions":[{"id":"https://openalex.org/I2802519937","display_name":"Institut de Recherche en Informatique et Syst\u00e8mes Al\u00e9atoires","ror":"https://ror.org/00myn0z94","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I205703379","https://openalex.org/I2802204017","https://openalex.org/I2802519937","https://openalex.org/I28221208","https://openalex.org/I4210127572","https://openalex.org/I4210159245","https://openalex.org/I56067802"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"P. Quinton","raw_affiliation_strings":["Campus de Beaulieu, IRISA, Rennes, France","IRISA, Rennes, France"],"affiliations":[{"raw_affiliation_string":"Campus de Beaulieu, IRISA, Rennes, France","institution_ids":["https://openalex.org/I2802519937"]},{"raw_affiliation_string":"IRISA, Rennes, France","institution_ids":["https://openalex.org/I2802519937"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108108765","display_name":"Tanguy Risset","orcid":null},"institutions":[{"id":"https://openalex.org/I1326498283","display_name":"Institut national de recherche en sciences et technologies du num\u00e9rique","ror":"https://ror.org/02kvxyf05","country_code":"FR","type":"government","lineage":["https://openalex.org/I1326498283"]},{"id":"https://openalex.org/I113428412","display_name":"\u00c9cole Normale Sup\u00e9rieure de Lyon","ror":"https://ror.org/04zmssz18","country_code":"FR","type":"education","lineage":["https://openalex.org/I113428412","https://openalex.org/I203339264"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"T. Risset","raw_affiliation_strings":["Lip, ENS-Lyon, INRIA, Lyon, France","Ecole Normale Superi\u00e9ure de Lyon"],"affiliations":[{"raw_affiliation_string":"Lip, ENS-Lyon, INRIA, Lyon, France","institution_ids":["https://openalex.org/I113428412","https://openalex.org/I1326498283"]},{"raw_affiliation_string":"Ecole Normale Superi\u00e9ure de Lyon","institution_ids":["https://openalex.org/I113428412"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5046599885"],"corresponding_institution_ids":["https://openalex.org/I2802519937"],"apc_list":null,"apc_paid":null,"fwci":2.1064,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":{"value":0.86898082,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"22","issue":null,"first_page":"40","last_page":"50"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8252339363098145},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7693013548851013},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6883624792098999},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6750742197036743},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6012796759605408},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5763901472091675},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5667575001716614},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5495350956916809},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.5332132577896118},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.5077391862869263},{"id":"https://openalex.org/keywords/simd","display_name":"SIMD","score":0.503689706325531},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.4750673472881317},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.469127893447876},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.443021684885025},{"id":"https://openalex.org/keywords/multidimensional-systems","display_name":"Multidimensional systems","score":0.4387018382549286},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3252714276313782},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.19868382811546326},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.08922260999679565},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.08181124925613403}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8252339363098145},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.7693013548851013},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6883624792098999},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6750742197036743},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6012796759605408},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5763901472091675},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5667575001716614},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5495350956916809},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.5332132577896118},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.5077391862869263},{"id":"https://openalex.org/C150552126","wikidata":"https://www.wikidata.org/wiki/Q339387","display_name":"SIMD","level":2,"score":0.503689706325531},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.4750673472881317},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.469127893447876},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.443021684885025},{"id":"https://openalex.org/C158457486","wikidata":"https://www.wikidata.org/wiki/Q17104301","display_name":"Multidimensional systems","level":2,"score":0.4387018382549286},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3252714276313782},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.19868382811546326},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.08922260999679565},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.08181124925613403},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asap.2003.1212828","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2003.1212828","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4000000059604645,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1497684279","https://openalex.org/W1583386943","https://openalex.org/W1862170100","https://openalex.org/W1970141743","https://openalex.org/W1975104688","https://openalex.org/W2002252837","https://openalex.org/W2010109834","https://openalex.org/W2010196134","https://openalex.org/W2014892800","https://openalex.org/W2038495591","https://openalex.org/W2082711009","https://openalex.org/W2098809996","https://openalex.org/W2107348617","https://openalex.org/W2107378533","https://openalex.org/W2116144668","https://openalex.org/W2157413058","https://openalex.org/W2506054026","https://openalex.org/W2744291701","https://openalex.org/W2983923412","https://openalex.org/W4230473729","https://openalex.org/W6629699859","https://openalex.org/W6634784020","https://openalex.org/W6742840386"],"related_works":["https://openalex.org/W4250699891","https://openalex.org/W2160542743","https://openalex.org/W2146636354","https://openalex.org/W3002976045","https://openalex.org/W4247178515","https://openalex.org/W1981284526","https://openalex.org/W2097236935","https://openalex.org/W1843355381","https://openalex.org/W1492116303","https://openalex.org/W2069295582"],"abstract_inverted_index":{"We":[0,40,56],"introduce":[1],"some":[2],"basic":[3],"principles":[4],"for":[5,50,62,100],"extending":[6],"the":[7,33,38,97],"classical":[8],"systolic":[9],"synthesis":[10,99],"methodology":[11],"to":[12,26,43,96],"multidimensional":[13,70,101],"time.":[14,102],"Multidimensional":[15],"scheduling":[16],"enables":[17],"complex":[18],"algorithms":[19],"that":[20,67],"do":[21],"not":[22],"admit":[23],"linear":[24],"schedules":[25],"be":[27],"parallelized,":[28],"but":[29],"it":[30],"also":[31,57],"requires":[32],"use":[34],"of":[35],"memories":[36],"in":[37],"architecture.":[39],"explain":[41],"how":[42],"obtain":[44],"compatible":[45],"allocation":[46],"and":[47,79],"memory":[48],"functions":[49],"VLSI":[51,65],"(or":[52],"SIMD-like":[53],"code)":[54],"generation.":[55],"present":[58],"an":[59],"original":[60],"mechanism":[61],"controlling":[63],"a":[64,69],"architecture":[66],"has":[68,76],"schedule.":[71],"A":[72],"structural":[73],"VHDL":[74],"code":[75],"been":[77],"derived":[78],"synthesized":[80],"(for":[81],"implementation":[82],"on":[83],"FPGA":[84],"platforms)":[85],"using":[86],"these":[87],"systematic":[88],"design":[89],"principles.":[90],"These":[91],"results":[92],"are":[93],"preliminary":[94],"steps":[95],"hardware":[98]},"counts_by_year":[{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
