{"id":"https://openalex.org/W2892053304","doi":"https://doi.org/10.1109/arith.2018.8464695","title":"High Density and Performance Multiplication for FPGA","display_name":"High Density and Performance Multiplication for FPGA","publication_year":2018,"publication_date":"2018-06-01","ids":{"openalex":"https://openalex.org/W2892053304","doi":"https://doi.org/10.1109/arith.2018.8464695","mag":"2892053304"},"language":"en","primary_location":{"id":"doi:10.1109/arith.2018.8464695","is_oa":false,"landing_page_url":"https://doi.org/10.1109/arith.2018.8464695","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE 25th Symposium on Computer Arithmetic (ARITH)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082265695","display_name":"Martin Langhammer","orcid":"https://orcid.org/0000-0001-8206-2077"},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Martin Langhammer","raw_affiliation_strings":["Intel UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel UK","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5067241056","display_name":"Gregg Baeckler","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gregg Baeckler","raw_affiliation_strings":["Intel US"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel US","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.4403,"has_fulltext":false,"cited_by_count":25,"citation_normalized_percentile":{"value":0.83194564,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"5","last_page":"12"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.8516174554824829},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7385905981063843},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7375580072402954},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.6373881697654724},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.5960935950279236},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.570239245891571},{"id":"https://openalex.org/keywords/multiplication","display_name":"Multiplication (music)","score":0.46056419610977173},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.4364981949329376},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.37186145782470703},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.36526232957839966},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.27104365825653076},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.16519424319267273}],"concepts":[{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.8516174554824829},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7385905981063843},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7375580072402954},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.6373881697654724},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.5960935950279236},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.570239245891571},{"id":"https://openalex.org/C2780595030","wikidata":"https://www.wikidata.org/wiki/Q3860309","display_name":"Multiplication (music)","level":2,"score":0.46056419610977173},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.4364981949329376},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.37186145782470703},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.36526232957839966},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.27104365825653076},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.16519424319267273},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/arith.2018.8464695","is_oa":false,"landing_page_url":"https://doi.org/10.1109/arith.2018.8464695","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE 25th Symposium on Computer Arithmetic (ARITH)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5199999809265137,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1605020135","https://openalex.org/W1996817998","https://openalex.org/W2026445983","https://openalex.org/W2048773562","https://openalex.org/W2052363354","https://openalex.org/W2061488635","https://openalex.org/W2521740029"],"related_works":["https://openalex.org/W2187189666","https://openalex.org/W2949084706","https://openalex.org/W631639522","https://openalex.org/W2754841804","https://openalex.org/W2818116514","https://openalex.org/W4226341794","https://openalex.org/W2306407715","https://openalex.org/W2382457518","https://openalex.org/W4386159357","https://openalex.org/W2789072850"],"abstract_inverted_index":{"Arithmetic":[0],"based":[1],"applications":[2],"are":[3,56,85,134,147,155],"one":[4],"of":[5,51,54,91,143,168,192],"the":[6,20,43,57,95,116,130,141,190],"most":[7,98],"common":[8,69],"use":[9,199],"cases":[10],"for":[11,24,87,100,109,122,126,136,172,196],"modern":[12],"FPGAs.":[13],"Currently,":[14],"machine":[15,111],"learning":[16,112],"is":[17,35,81,97,106],"emerging":[18],"as":[19,161,163],"fastest":[21],"growth":[22],"area":[23],"FPG":[25],"As,":[26],"renewing":[27],"an":[28],"interest":[29],"in":[30,42,189],"low":[31],"precision":[32],"multiplication.":[33],"There":[34],"now":[36],"a":[37,88,177,184],"new":[38],"focus":[39],"on":[40],"multiplication":[41],"soft":[44],"fabric":[45],"-":[46],"very":[47],"high-density":[48],"systems,":[49],"consisting":[50],"many":[52],"thousands":[53],"operations,":[55],"current":[58],"norm.":[59],"In":[60],"this":[61],"paper":[62],"we":[63],"introduce":[64],"multiplier":[65,70,79,105],"regularization,":[66],"which":[67],"restructures":[68],"algorithms":[71],"into":[72],"smaller,":[73],"and":[74,83,115,183],"more":[75,185],"efficient":[76,99],"architectures.":[77,153],"The":[78,104],"structure":[80],"parameterizable,":[82],"results":[84,171],"given":[86],"continuous":[89],"range":[90,191],"input":[92,102],"sizes,":[93],"although":[94],"algorithm":[96],"small":[101],"precisions.":[103],"particularly":[107],"effective":[108],"typical":[110,197],"inferencing":[113,198],"uses,":[114],"presented":[117,132],"cores":[118],"can":[119],"be":[120],"used":[121],"dot":[123],"products":[124],"required":[125],"these":[127],"applications.":[128],"Although":[129],"examples":[131],"here":[133],"optimized":[135],"Intel":[137,158],"Stratix":[138],"10":[139],"devices,":[140],"concept":[142],"regularized":[144],"arithmetic":[145],"structures":[146],"applicable":[148],"to":[149,157,179,194],"generic":[150],"FPGA":[151],"LUT":[152],"Results":[154],"compared":[156],"Megafunction":[159],"IP":[160],"well":[162],"contrasted":[164],"with":[165],"normalized":[166],"representations":[167],"recently":[169],"published":[170],"Xilinx":[173],"devices.":[174],"We":[175],"report":[176],"10%":[178],"35%":[180],"smaller":[181],"area,":[182],"significant":[186],"latency":[187],"reduction,":[188],"25%":[193],"50%,":[195],"cases.":[200]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":4}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
