{"id":"https://openalex.org/W1924196901","doi":"https://doi.org/10.1109/arith.2003.1207688","title":"Energy-delay estimation technique for high-performance microprocessor VLSI adders","display_name":"Energy-delay estimation technique for high-performance microprocessor VLSI adders","publication_year":2004,"publication_date":"2004-03-22","ids":{"openalex":"https://openalex.org/W1924196901","doi":"https://doi.org/10.1109/arith.2003.1207688","mag":"1924196901"},"language":"en","primary_location":{"id":"doi:10.1109/arith.2003.1207688","is_oa":false,"landing_page_url":"https://doi.org/10.1109/arith.2003.1207688","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th IEEE Symposium on Computer Arithmetic, 2003. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010898738","display_name":"Vojin G. Oklobdzija","orcid":null},"institutions":[{"id":"https://openalex.org/I84218800","display_name":"University of California, Davis","ror":"https://ror.org/05rrcem69","country_code":"US","type":"education","lineage":["https://openalex.org/I84218800"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"V.G. Oklobdzija","raw_affiliation_strings":["ACSEL, University of California, Davis, CA, USA","California Univ., Davis, CA (USA)"],"affiliations":[{"raw_affiliation_string":"ACSEL, University of California, Davis, CA, USA","institution_ids":["https://openalex.org/I84218800"]},{"raw_affiliation_string":"California Univ., Davis, CA (USA)","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062361284","display_name":"B.R. Zeydel","orcid":null},"institutions":[{"id":"https://openalex.org/I84218800","display_name":"University of California, Davis","ror":"https://ror.org/05rrcem69","country_code":"US","type":"education","lineage":["https://openalex.org/I84218800"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"B.R. Zeydel","raw_affiliation_strings":["ACSEL, University of California, Davis, CA, USA","California Univ., Davis, CA (USA)"],"affiliations":[{"raw_affiliation_string":"ACSEL, University of California, Davis, CA, USA","institution_ids":["https://openalex.org/I84218800"]},{"raw_affiliation_string":"California Univ., Davis, CA (USA)","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091651695","display_name":"H.Q. Dao","orcid":null},"institutions":[{"id":"https://openalex.org/I84218800","display_name":"University of California, Davis","ror":"https://ror.org/05rrcem69","country_code":"US","type":"education","lineage":["https://openalex.org/I84218800"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"H. Dao","raw_affiliation_strings":["ACSEL, University of California, Davis, CA, USA","California Univ., Davis, CA (USA)"],"affiliations":[{"raw_affiliation_string":"ACSEL, University of California, Davis, CA, USA","institution_ids":["https://openalex.org/I84218800"]},{"raw_affiliation_string":"California Univ., Davis, CA (USA)","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039276616","display_name":"Sanu Mathew","orcid":"https://orcid.org/0000-0003-1344-7533"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Mathew","raw_affiliation_strings":["Circuit Research Laboratories, Intel Corporation, Hillsboro, OR, USA","Circuit Res. Labs, Intel Corp., Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Circuit Research Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Circuit Res. Labs, Intel Corp., Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074107306","display_name":"Ram Krishnamurthy","orcid":"https://orcid.org/0000-0002-2428-7099"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ram Krishnamurthy","raw_affiliation_strings":["Circuit Research Laboratories, Intel Corporation, Hillsboro, OR, USA","Circuit Res. Labs, Intel Corp., Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Circuit Research Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Circuit Res. Labs, Intel Corp., Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5010898738"],"corresponding_institution_ids":["https://openalex.org/I84218800"],"apc_list":null,"apc_paid":null,"fwci":8.8084,"has_fulltext":false,"cited_by_count":68,"citation_normalized_percentile":{"value":0.98037614,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"272","last_page":"279"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9507509469985962},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.8186074495315552},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7397086024284363},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.676481306552887},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.5967689156532288},{"id":"https://openalex.org/keywords/energy","display_name":"Energy (signal processing)","score":0.587892472743988},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5101092457771301},{"id":"https://openalex.org/keywords/efficient-energy-use","display_name":"Efficient energy use","score":0.49929141998291016},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.4289349913597107},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3310697078704834},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.22142598032951355},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.21905186772346497},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1594860851764679},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.13144639134407043}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9507509469985962},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.8186074495315552},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7397086024284363},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.676481306552887},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.5967689156532288},{"id":"https://openalex.org/C186370098","wikidata":"https://www.wikidata.org/wiki/Q442787","display_name":"Energy (signal processing)","level":2,"score":0.587892472743988},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5101092457771301},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.49929141998291016},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.4289349913597107},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3310697078704834},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.22142598032951355},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.21905186772346497},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1594860851764679},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.13144639134407043},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/arith.2003.1207688","is_oa":false,"landing_page_url":"https://doi.org/10.1109/arith.2003.1207688","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th IEEE Symposium on Computer Arithmetic, 2003. Proceedings.","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.71.4211","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.71.4211","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_Oklobdzija.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.89.4234","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.89.4234","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ece.ucdavis.edu/~brzeydel/Publications/1-ARITH-2003.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8899999856948853,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W74751774","https://openalex.org/W1817545098","https://openalex.org/W1879578558","https://openalex.org/W1963965124","https://openalex.org/W2058254562","https://openalex.org/W2086429465","https://openalex.org/W2088115909","https://openalex.org/W2097414281","https://openalex.org/W2104733895","https://openalex.org/W2131647018","https://openalex.org/W2133247319","https://openalex.org/W2143462372","https://openalex.org/W2789135052","https://openalex.org/W6603007428","https://openalex.org/W6664822897","https://openalex.org/W6681009940"],"related_works":["https://openalex.org/W4390550886","https://openalex.org/W3217463396","https://openalex.org/W2790557758","https://openalex.org/W2516396101","https://openalex.org/W3204929712","https://openalex.org/W4295102875","https://openalex.org/W2300671402","https://openalex.org/W4312888585","https://openalex.org/W2533938775","https://openalex.org/W2015155483"],"abstract_inverted_index":{"We":[0],"motivate":[1],"the":[2,19,38],"concept":[3],"of":[4,22,59],"comparing":[5],"VLSI":[6,25],"adders":[7,47],"based":[8],"on":[9],"their":[10],"energy-delay":[11,20,39],"trade-offs":[12],"and":[13,44,51,64],"present":[14],"a":[15],"technique":[16],"for":[17,41],"estimating":[18],"space":[21,40],"various":[23],"high-performance":[24,42],"adder":[26],"topologies.":[27],"Further,":[28],"we":[29],"show":[30],"that":[31],"our":[32],"estimates":[33,63],"accurately":[34],"represent":[35],"tradeoffs":[36],"in":[37,48,61,66],"32-bit":[43],"64-bit":[45],"processor":[46],"0.13/spl":[49],"mu/m":[50,53],"0.10/spl":[52],"CMOS":[54],"technologies,":[55],"with":[56,70],"an":[57],"accuracy":[58],"8%":[60],"delay":[62],"20%":[65],"energy":[67],"estimates,":[68],"compared":[69],"simulated":[71],"data.":[72]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}