{"id":"https://openalex.org/W7130536995","doi":"https://doi.org/10.1109/apccas67402.2025.11377100","title":"FCP-LLM: Functional Coverpoint Plan Generation Using LLM in Early Design Verification Stage","display_name":"FCP-LLM: Functional Coverpoint Plan Generation Using LLM in Early Design Verification Stage","publication_year":2025,"publication_date":"2025-10-12","ids":{"openalex":"https://openalex.org/W7130536995","doi":"https://doi.org/10.1109/apccas67402.2025.11377100"},"language":null,"primary_location":{"id":"doi:10.1109/apccas67402.2025.11377100","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas67402.2025.11377100","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026532546","display_name":"Zhuofan Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Zhuofan Lin","raw_affiliation_strings":["Shanghai Jiao Tong University,Department of Micro-Nano Electronics,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Shanghai Jiao Tong University,Department of Micro-Nano Electronics,China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102645415","display_name":"Zixian Guo","orcid":null},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zixian Guo","raw_affiliation_strings":["Shanghai Jiao Tong University,Department of Micro-Nano Electronics,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Shanghai Jiao Tong University,Department of Micro-Nano Electronics,China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5126438975","display_name":"Chao Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chao Wang","raw_affiliation_strings":["Shanghai Jiao Tong University,Department of Micro-Nano Electronics,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Shanghai Jiao Tong University,Department of Micro-Nano Electronics,China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020011546","display_name":"Ruixin Zheng","orcid":null},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ruixin Zheng","raw_affiliation_strings":["Shanghai Jiao Tong University,Department of Micro-Nano Electronics,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Shanghai Jiao Tong University,Department of Micro-Nano Electronics,China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5124117366","display_name":"Yuxin Ji","orcid":null},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuxin Ji","raw_affiliation_strings":["Shanghai Jiao Tong University,Department of Micro-Nano Electronics,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Shanghai Jiao Tong University,Department of Micro-Nano Electronics,China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024183398","display_name":"Yang Wei Lim","orcid":"https://orcid.org/0000-0001-8949-5203"},"institutions":[{"id":"https://openalex.org/I130343225","display_name":"Universiti Putra Malaysia","ror":"https://ror.org/02e91jd64","country_code":"MY","type":"education","lineage":["https://openalex.org/I130343225"]}],"countries":["MY"],"is_corresponding":false,"raw_author_name":"Yang Wei Lim","raw_affiliation_strings":["University Putra Malaysia,Department of Computer and Communication Systems Engineering,Malaysia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University Putra Malaysia,Department of Computer and Communication Systems Engineering,Malaysia","institution_ids":["https://openalex.org/I130343225"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070118708","display_name":"Y. H. Zhang","orcid":"https://orcid.org/0009-0001-7814-005X"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuhang Zhang","raw_affiliation_strings":["Shanghai Jiao Tong University,Department of Micro-Nano Electronics,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Shanghai Jiao Tong University,Department of Micro-Nano Electronics,China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Fakhrul Zaman Rokhani","orcid":null},"institutions":[{"id":"https://openalex.org/I130343225","display_name":"Universiti Putra Malaysia","ror":"https://ror.org/02e91jd64","country_code":"MY","type":"education","lineage":["https://openalex.org/I130343225"]}],"countries":["MY"],"is_corresponding":false,"raw_author_name":"Fakhrul Zaman Rokhani","raw_affiliation_strings":["University Putra Malaysia,Department of Computer and Communication Systems Engineering,Malaysia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University Putra Malaysia,Department of Computer and Communication Systems Engineering,Malaysia","institution_ids":["https://openalex.org/I130343225"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5126402263","display_name":"Yongfu Li","orcid":null},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yongfu Li","raw_affiliation_strings":["Shanghai Jiao Tong University,Department of Micro-Nano Electronics,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Shanghai Jiao Tong University,Department of Micro-Nano Electronics,China","institution_ids":["https://openalex.org/I183067930"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":9,"corresponding_author_ids":["https://openalex.org/A5026532546"],"corresponding_institution_ids":["https://openalex.org/I183067930"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.75298988,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.5284000039100647,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.5284000039100647,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.27300000190734863,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.03970000147819519,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.6366999745368958},{"id":"https://openalex.org/keywords/plan","display_name":"Plan (archaeology)","score":0.574400007724762},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5085999965667725},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.4880000054836273},{"id":"https://openalex.org/keywords/focus","display_name":"Focus (optics)","score":0.4499000012874603},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.4287000000476837},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.39010000228881836},{"id":"https://openalex.org/keywords/engineering-design-process","display_name":"Engineering design process","score":0.36059999465942383},{"id":"https://openalex.org/keywords/baseline","display_name":"Baseline (sea)","score":0.35510000586509705}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7044000029563904},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.6366999745368958},{"id":"https://openalex.org/C2776505523","wikidata":"https://www.wikidata.org/wiki/Q4785468","display_name":"Plan (archaeology)","level":2,"score":0.574400007724762},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5085999965667725},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.4880000054836273},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.4740999937057495},{"id":"https://openalex.org/C192209626","wikidata":"https://www.wikidata.org/wiki/Q190909","display_name":"Focus (optics)","level":2,"score":0.4499000012874603},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.43050000071525574},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.4287000000476837},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.39010000228881836},{"id":"https://openalex.org/C34972735","wikidata":"https://www.wikidata.org/wiki/Q2920267","display_name":"Engineering design process","level":2,"score":0.36059999465942383},{"id":"https://openalex.org/C12725497","wikidata":"https://www.wikidata.org/wiki/Q810247","display_name":"Baseline (sea)","level":2,"score":0.35510000586509705},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.3472000062465668},{"id":"https://openalex.org/C2982740150","wikidata":"https://www.wikidata.org/wiki/Q5249230","display_name":"Design cycle","level":2,"score":0.34119999408721924},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.33559998869895935},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.32820001244544983},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.30709999799728394},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.30649998784065247},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.30300000309944153},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.29910001158714294},{"id":"https://openalex.org/C48262172","wikidata":"https://www.wikidata.org/wiki/Q16908765","display_name":"Design process","level":3,"score":0.29760000109672546},{"id":"https://openalex.org/C55396564","wikidata":"https://www.wikidata.org/wiki/Q3084971","display_name":"Process design","level":3,"score":0.28929999470710754},{"id":"https://openalex.org/C199639397","wikidata":"https://www.wikidata.org/wiki/Q1788588","display_name":"Engineering drawing","level":1,"score":0.2883000075817108},{"id":"https://openalex.org/C2988963302","wikidata":"https://www.wikidata.org/wiki/Q629206","display_name":"Program code","level":2,"score":0.2727999985218048},{"id":"https://openalex.org/C207850805","wikidata":"https://www.wikidata.org/wiki/Q269608","display_name":"Reverse engineering","level":2,"score":0.2712000012397766},{"id":"https://openalex.org/C2779089604","wikidata":"https://www.wikidata.org/wiki/Q7169333","display_name":"Permission","level":2,"score":0.26579999923706055},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.2639000117778778},{"id":"https://openalex.org/C18762648","wikidata":"https://www.wikidata.org/wiki/Q42213","display_name":"Work (physics)","level":2,"score":0.26030001044273376},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.2535000145435333}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas67402.2025.11377100","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas67402.2025.11377100","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.48896628618240356,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1925060989","https://openalex.org/W2042079791","https://openalex.org/W3119041485","https://openalex.org/W3130437014","https://openalex.org/W4210725750","https://openalex.org/W4252251132","https://openalex.org/W4309674289","https://openalex.org/W4389166737","https://openalex.org/W4392405447","https://openalex.org/W4403023622","https://openalex.org/W4403024143","https://openalex.org/W4404134046","https://openalex.org/W4405846333"],"related_works":[],"abstract_inverted_index":{"During":[0],"the":[1,18,48,88,120],"design":[2,41,57],"process":[3],"of":[4,34,71,76,103,127],"digital":[5,111],"integrated":[6],"circuits,":[7,105],"high-quality":[8],"coverpoint":[9,83,139],"plan":[10,140],"plays":[11],"a":[12,31,101,131],"crucial":[13],"role,":[14],"as":[15],"it":[16],"guides":[17],"verification":[19],"process.":[20],"This":[21],"challenging":[22],"task":[23],"is":[24,52],"accomplished":[25],"by":[26],"experienced":[27],"engineers":[28],"who":[29],"consume":[30],"massive":[32],"amount":[33],"time":[35],"to":[36,54,65],"extract":[37],"critical":[38,69],"information":[39],"from":[40],"specifications.":[42],"In":[43],"this":[44],"work,":[45],"we":[46],"present":[47],"FCP-LLM":[49,118],"framework":[50],"that":[51,117],"designed":[53],"understand":[55],"both":[56],"specifications":[58],"and":[59,90,109,136],"Hardware":[60],"Description":[61],"Language":[62],"(HDL)":[63],"code":[64],"focus":[66],"on":[67],"extracting":[68],"edges":[70],"designs'":[72],"ports.":[73],"It":[74,96],"consists":[75],"three":[77],"main":[78],"components:":[79],"CP-Generator":[80],"for":[81,86,92],"creating":[82],"plans,":[84,89],"CP-Reviewer":[85],"refining":[87],"SV-Coder":[91],"generating":[93],"SystemVerilog":[94],"code.":[95],"has":[97],"been":[98],"evaluated":[99],"with":[100,123],"series":[102],"benchmark":[104],"comprising":[106],"74X-Series":[107],"circuits":[108],"custom":[110],"designs.":[112],"Our":[113],"experimental":[114],"results":[115],"show":[116],"outperforms":[119],"baseline":[121],"work":[122],"an":[124],"average":[125],"improvement":[126],"exceeding":[128],"300%,":[129],"demonstrating":[130],"better":[132],"balance":[133],"between":[134],"effectiveness":[135],"redundancy":[137],"in":[138],"generation.":[141]},"counts_by_year":[],"updated_date":"2026-05-05T08:41:31.759640","created_date":"2026-02-20T00:00:00"}