{"id":"https://openalex.org/W4405845980","doi":"https://doi.org/10.1109/apccas62602.2024.10808772","title":"The VLSI Architecture Design of a Configurable and High-Throughput Singular Value Decomposition Processor","display_name":"The VLSI Architecture Design of a Configurable and High-Throughput Singular Value Decomposition Processor","publication_year":2024,"publication_date":"2024-11-07","ids":{"openalex":"https://openalex.org/W4405845980","doi":"https://doi.org/10.1109/apccas62602.2024.10808772"},"language":"en","primary_location":{"id":"doi:10.1109/apccas62602.2024.10808772","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas62602.2024.10808772","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5104133681","display_name":"Tien-Min Chang","orcid":null},"institutions":[{"id":"https://openalex.org/I154864474","display_name":"National Taiwan University of Science and Technology","ror":"https://ror.org/00q09pe49","country_code":"TW","type":"education","lineage":["https://openalex.org/I154864474"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Tien-Min Chang","raw_affiliation_strings":["National Taiwan University of Science and Technology,Department of Electronic and Computer Engineering,Taipei,Taiwan"],"affiliations":[{"raw_affiliation_string":"National Taiwan University of Science and Technology,Department of Electronic and Computer Engineering,Taipei,Taiwan","institution_ids":["https://openalex.org/I154864474"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5019065083","display_name":"Chung-An Shen","orcid":"https://orcid.org/0000-0002-0628-5129"},"institutions":[{"id":"https://openalex.org/I154864474","display_name":"National Taiwan University of Science and Technology","ror":"https://ror.org/00q09pe49","country_code":"TW","type":"education","lineage":["https://openalex.org/I154864474"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chung-An Shen","raw_affiliation_strings":["National Taiwan University of Science and Technology,Department of Electronic and Computer Engineering,Taipei,Taiwan"],"affiliations":[{"raw_affiliation_string":"National Taiwan University of Science and Technology,Department of Electronic and Computer Engineering,Taipei,Taiwan","institution_ids":["https://openalex.org/I154864474"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5104133681"],"corresponding_institution_ids":["https://openalex.org/I154864474"],"apc_list":null,"apc_paid":null,"fwci":0.5319,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.68959229,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"519","last_page":"523"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9945999979972839,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9886999726295471,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7769526243209839},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.6792584657669067},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6714844703674316},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6669032573699951},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6480181217193604},{"id":"https://openalex.org/keywords/singular-value-decomposition","display_name":"Singular value decomposition","score":0.5754978656768799},{"id":"https://openalex.org/keywords/decomposition","display_name":"Decomposition","score":0.5600350499153137},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5191275477409363},{"id":"https://openalex.org/keywords/value","display_name":"Value (mathematics)","score":0.5008459091186523},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.30302298069000244},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.09035295248031616},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08477333188056946}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7769526243209839},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.6792584657669067},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6714844703674316},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6669032573699951},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6480181217193604},{"id":"https://openalex.org/C22789450","wikidata":"https://www.wikidata.org/wiki/Q420904","display_name":"Singular value decomposition","level":2,"score":0.5754978656768799},{"id":"https://openalex.org/C124681953","wikidata":"https://www.wikidata.org/wiki/Q339062","display_name":"Decomposition","level":2,"score":0.5600350499153137},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5191275477409363},{"id":"https://openalex.org/C2776291640","wikidata":"https://www.wikidata.org/wiki/Q2912517","display_name":"Value (mathematics)","level":2,"score":0.5008459091186523},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.30302298069000244},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.09035295248031616},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08477333188056946},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas62602.2024.10808772","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas62602.2024.10808772","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1494785017","https://openalex.org/W2091892586","https://openalex.org/W2759196273","https://openalex.org/W2800993807","https://openalex.org/W2893324634","https://openalex.org/W2980731865","https://openalex.org/W3008933927","https://openalex.org/W3029162182","https://openalex.org/W4206821030","https://openalex.org/W4311411094"],"related_works":["https://openalex.org/W4283025278","https://openalex.org/W3121932492","https://openalex.org/W4232638561","https://openalex.org/W61292821","https://openalex.org/W2082432309","https://openalex.org/W817174743","https://openalex.org/W2050492524","https://openalex.org/W2134640991","https://openalex.org/W3027318491","https://openalex.org/W101478184"],"abstract_inverted_index":{"This":[0],"paper":[1,31],"presents":[2],"the":[3,33,52,59,68,75,88,105,110,121,136,138,143],"algorithm":[4,27,54],"and":[5,37,55,85],"VLSI":[6],"architecture":[7,47],"of":[8,19,35,62,95,112,123,128],"a":[9],"high-throughput":[10,42],"singular":[11],"value":[12],"decomposition":[13],"(SVD)":[14],"processor":[15,82],"that":[16,109],"decomposes":[17],"matrices":[18,115],"any":[20],"size,":[21],"including":[22],"nonsquare":[23],"matrices.":[24],"The":[25,45,79,100],"SVD":[26,46,81,140],"presented":[28],"in":[29,126,135],"this":[30],"reduces":[32],"number":[34],"iterations":[36],"is":[38,48,65,71,83,118],"more":[39],"suitable":[40],"for":[41],"engine":[43,141],"design.":[44],"designed":[49,84],"based":[50,103],"on":[51,104],"proposed":[53,80,139],"processing":[56,69],"flow,":[57],"where":[58],"hardware":[60],"utilization":[61],"computing":[63],"units":[64],"enhanced.":[66],"Thus,":[67],"throughput":[70,111],"greatly":[72],"enhanced":[73],"while":[74],"complexity":[76],"remains":[77],"manageable.":[78],"implemented":[86],"with":[87,132],"application-specific":[89],"integrated":[90],"circuits":[91],"(ASIC)":[92],"design":[93],"flow":[94],"CMOS":[96],"90":[97],"nm":[98],"technology.":[99],"performance":[101],"estimations":[102],"post-layout":[106],"simulations":[107],"show":[108],"15384.6":[113],"k":[114],"per":[116],"second":[117],"achieved":[119],"at":[120],"cost":[122],"210.64":[124],"kGE":[125],"terms":[127],"NAND":[129],"gates.":[130],"Compared":[131],"designs":[133],"reported":[134],"literature,":[137],"enhances":[142],"efficiency":[144],"by":[145],"33%.":[146]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2025-12-21T01:58:51.020947","created_date":"2025-10-10T00:00:00"}
