{"id":"https://openalex.org/W4405845987","doi":"https://doi.org/10.1109/apccas62602.2024.10808656","title":"Physical Design of RISC-V based System-on-Chip using OpenLane","display_name":"Physical Design of RISC-V based System-on-Chip using OpenLane","publication_year":2024,"publication_date":"2024-11-07","ids":{"openalex":"https://openalex.org/W4405845987","doi":"https://doi.org/10.1109/apccas62602.2024.10808656"},"language":"en","primary_location":{"id":"doi:10.1109/apccas62602.2024.10808656","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas62602.2024.10808656","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101695767","display_name":"Muhammad Fauzan","orcid":"https://orcid.org/0009-0009-9198-3594"},"institutions":[{"id":"https://openalex.org/I134635517","display_name":"Bandung Institute of Technology","ror":"https://ror.org/00apj8t60","country_code":"ID","type":"education","lineage":["https://openalex.org/I134635517"]}],"countries":["ID"],"is_corresponding":true,"raw_author_name":"Muhammad Fauzan","raw_affiliation_strings":["Bandung Institute of Technology,School of Electrical Engineering and Informatics,Indonesia"],"affiliations":[{"raw_affiliation_string":"Bandung Institute of Technology,School of Electrical Engineering and Informatics,Indonesia","institution_ids":["https://openalex.org/I134635517"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5115676467","display_name":"Raihan Fadhil Yanuarsyah","orcid":null},"institutions":[{"id":"https://openalex.org/I134635517","display_name":"Bandung Institute of Technology","ror":"https://ror.org/00apj8t60","country_code":"ID","type":"education","lineage":["https://openalex.org/I134635517"]}],"countries":["ID"],"is_corresponding":false,"raw_author_name":"Raihan Fadhil Yanuarsyah","raw_affiliation_strings":["Bandung Institute of Technology,School of Electrical Engineering and Informatics,Indonesia"],"affiliations":[{"raw_affiliation_string":"Bandung Institute of Technology,School of Electrical Engineering and Informatics,Indonesia","institution_ids":["https://openalex.org/I134635517"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5115676468","display_name":"Muhammad Hanif Hibatullah","orcid":null},"institutions":[{"id":"https://openalex.org/I134635517","display_name":"Bandung Institute of Technology","ror":"https://ror.org/00apj8t60","country_code":"ID","type":"education","lineage":["https://openalex.org/I134635517"]}],"countries":["ID"],"is_corresponding":false,"raw_author_name":"Muhammad Hanif Hibatullah","raw_affiliation_strings":["Bandung Institute of Technology,School of Electrical Engineering and Informatics,Indonesia"],"affiliations":[{"raw_affiliation_string":"Bandung Institute of Technology,School of Electrical Engineering and Informatics,Indonesia","institution_ids":["https://openalex.org/I134635517"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5115676469","display_name":"Radithya Arisaputra","orcid":null},"institutions":[{"id":"https://openalex.org/I134635517","display_name":"Bandung Institute of Technology","ror":"https://ror.org/00apj8t60","country_code":"ID","type":"education","lineage":["https://openalex.org/I134635517"]}],"countries":["ID"],"is_corresponding":false,"raw_author_name":"Radithya Arisaputra","raw_affiliation_strings":["Bandung Institute of Technology,School of Electrical Engineering and Informatics,Indonesia"],"affiliations":[{"raw_affiliation_string":"Bandung Institute of Technology,School of Electrical Engineering and Informatics,Indonesia","institution_ids":["https://openalex.org/I134635517"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038926636","display_name":"Infall Syafalni","orcid":"https://orcid.org/0000-0001-9922-5688"},"institutions":[{"id":"https://openalex.org/I134635517","display_name":"Bandung Institute of Technology","ror":"https://ror.org/00apj8t60","country_code":"ID","type":"education","lineage":["https://openalex.org/I134635517"]}],"countries":["ID"],"is_corresponding":false,"raw_author_name":"Infall Syafalni","raw_affiliation_strings":["Bandung Institute of Technology,School of Electrical Engineering and Informatics,Indonesia"],"affiliations":[{"raw_affiliation_string":"Bandung Institute of Technology,School of Electrical Engineering and Informatics,Indonesia","institution_ids":["https://openalex.org/I134635517"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059864105","display_name":"Nana Sutisna","orcid":"https://orcid.org/0000-0002-8435-9242"},"institutions":[{"id":"https://openalex.org/I134635517","display_name":"Bandung Institute of Technology","ror":"https://ror.org/00apj8t60","country_code":"ID","type":"education","lineage":["https://openalex.org/I134635517"]}],"countries":["ID"],"is_corresponding":false,"raw_author_name":"Nana Sutisna","raw_affiliation_strings":["Bandung Institute of Technology,School of Electrical Engineering and Informatics,Indonesia"],"affiliations":[{"raw_affiliation_string":"Bandung Institute of Technology,School of Electrical Engineering and Informatics,Indonesia","institution_ids":["https://openalex.org/I134635517"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019689855","display_name":"Trio Adiono","orcid":"https://orcid.org/0000-0003-4808-9254"},"institutions":[{"id":"https://openalex.org/I134635517","display_name":"Bandung Institute of Technology","ror":"https://ror.org/00apj8t60","country_code":"ID","type":"education","lineage":["https://openalex.org/I134635517"]}],"countries":["ID"],"is_corresponding":false,"raw_author_name":"Trio Adiono","raw_affiliation_strings":["Bandung Institute of Technology,School of Electrical Engineering and Informatics,Indonesia"],"affiliations":[{"raw_affiliation_string":"Bandung Institute of Technology,School of Electrical Engineering and Informatics,Indonesia","institution_ids":["https://openalex.org/I134635517"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102900006","display_name":"Makoto Ikeda","orcid":"https://orcid.org/0000-0002-6644-4224"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Makoto Ikeda","raw_affiliation_strings":["The University of Tokyo,System Design Laboratory School of Engineering,Tokyo,Japan"],"affiliations":[{"raw_affiliation_string":"The University of Tokyo,System Design Laboratory School of Engineering,Tokyo,Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5101695767"],"corresponding_institution_ids":["https://openalex.org/I134635517"],"apc_list":null,"apc_paid":null,"fwci":2.1979,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.89162093,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":98,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"529","last_page":"533"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9455000162124634,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9455000162124634,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9067000150680542,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.6925195455551147},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6790895462036133},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.6202049851417542},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5535875558853149},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5062429308891296},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.4638381600379944},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4291263222694397},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34705179929733276},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.31393569707870483},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.20134538412094116},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.19287016987800598},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0968727171421051}],"concepts":[{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.6925195455551147},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6790895462036133},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.6202049851417542},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5535875558853149},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5062429308891296},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.4638381600379944},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4291263222694397},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34705179929733276},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.31393569707870483},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.20134538412094116},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.19287016987800598},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0968727171421051}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas62602.2024.10808656","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas62602.2024.10808656","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W3200538824","https://openalex.org/W4283825335","https://openalex.org/W4388214728","https://openalex.org/W4389166704","https://openalex.org/W4390728566","https://openalex.org/W6787143565"],"related_works":["https://openalex.org/W2065289416","https://openalex.org/W2017236304","https://openalex.org/W2036644923","https://openalex.org/W2020934033","https://openalex.org/W4253195573","https://openalex.org/W2115579119","https://openalex.org/W2136854845","https://openalex.org/W2366617252","https://openalex.org/W2017475176","https://openalex.org/W2393788780"],"abstract_inverted_index":{"Open-source":[0],"tools":[1,20,115],"for":[2,8,98],"designing":[3,99],"integrated":[4],"circuits":[5],"are":[6,15],"crucial":[7],"electrical":[9],"engineering":[10],"students.":[11],"However,":[12],"more":[13],"references":[14],"necessary":[16],"to":[17,21],"promote":[18],"the":[19,22,37,48,84,100],"academic":[23,117],"environments.":[24,118],"This":[25],"paper":[26],"presents":[27],"design":[28,59,78,114],"and":[29,52,55,70,79,109],"implementation":[30],"of":[31,103],"a":[32],"PicoSoC":[33,43],"(Pico":[34],"System-on-Chip)":[35],"using":[36],"OpenLane":[38],"automated":[39],"VLSI":[40],"flow.":[41],"The":[42,58,73,94],"comprises":[44],"several":[45],"modules,":[46],"including":[47],"PicoRV32":[49],"CPU,":[50],"UART":[51],"SPI":[53],"peripherals,":[54],"memory":[56],"blocks.":[57],"methodology":[60],"encompasses":[61],"RTL":[62,92],"simulation,":[63],"macro":[64],"hardening,":[65,67,69],"core":[66],"full-chip":[68],"gatelevel":[71],"simulation.":[72,93],"results":[74],"indicate":[75],"successful":[76],"physical":[77,101],"functional":[80],"verification,":[81],"demonstrating":[82],"that":[83],"gate-level":[85],"simulation":[86],"outputs":[87],"align":[88],"with":[89],"those":[90],"from":[91],"work":[95],"is":[96],"useful":[97],"layout":[102],"digital":[104],"circuits,":[105],"SoC":[106],"architecture":[107],"development,":[108],"also":[110],"promoting":[111],"open-source":[112],"IC":[113],"in":[116]},"counts_by_year":[{"year":2025,"cited_by_count":6}],"updated_date":"2025-12-27T23:08:20.325037","created_date":"2025-10-10T00:00:00"}