{"id":"https://openalex.org/W4405845162","doi":"https://doi.org/10.1109/apccas62602.2024.10808655","title":"Accurate Estimation of Buffered Interconnect Delay Based on Virtual Buffering and Multi-Level Cluster Tree Techniques","display_name":"Accurate Estimation of Buffered Interconnect Delay Based on Virtual Buffering and Multi-Level Cluster Tree Techniques","publication_year":2024,"publication_date":"2024-11-07","ids":{"openalex":"https://openalex.org/W4405845162","doi":"https://doi.org/10.1109/apccas62602.2024.10808655"},"language":"en","primary_location":{"id":"doi:10.1109/apccas62602.2024.10808655","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas62602.2024.10808655","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5099073680","display_name":"Chen-Ho Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Chen-Ho Chen","raw_affiliation_strings":["Institute of Electronics National Yang Ming Chiao Tung University,Hsinchu,R.O.C"],"affiliations":[{"raw_affiliation_string":"Institute of Electronics National Yang Ming Chiao Tung University,Hsinchu,R.O.C","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052798292","display_name":"Chien\u2010Nan Jimmy Liu","orcid":"https://orcid.org/0000-0002-4907-898X"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chien-Nan Jimmy Liu","raw_affiliation_strings":["Institute of Electronics National Yang Ming Chiao Tung University,Hsinchu,R.O.C"],"affiliations":[{"raw_affiliation_string":"Institute of Electronics National Yang Ming Chiao Tung University,Hsinchu,R.O.C","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109376208","display_name":"Wei Tu","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Wei-Ting Tu","raw_affiliation_strings":["Synopsys Taiwan Co., Ltd.,Hsinchu,R.O.C"],"affiliations":[{"raw_affiliation_string":"Synopsys Taiwan Co., Ltd.,Hsinchu,R.O.C","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033920886","display_name":"Tung-Chieh Chen","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Tung-Chieh Chen","raw_affiliation_strings":["Synopsys Taiwan Co., Ltd.,Hsinchu,R.O.C"],"affiliations":[{"raw_affiliation_string":"Synopsys Taiwan Co., Ltd.,Hsinchu,R.O.C","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5031004106","display_name":"Iris Hui-Ru Jiang","orcid":"https://orcid.org/0000-0002-4554-3442"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Iris Hui-Ru Jiang","raw_affiliation_strings":["Graduate Institute of Electronics Engineering National Taiwan University,Taipei,R.O.C"],"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering National Taiwan University,Taipei,R.O.C","institution_ids":["https://openalex.org/I16733864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5099073680"],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.27902218,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"221","last_page":"225"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.988099992275238,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9811999797821045,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7227162718772888},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.614464521408081},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.5952391624450684},{"id":"https://openalex.org/keywords/cluster","display_name":"Cluster (spacecraft)","score":0.5539928674697876},{"id":"https://openalex.org/keywords/estimation","display_name":"Estimation","score":0.529246985912323},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.34425872564315796},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.24334850907325745},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1264469027519226},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09678393602371216}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7227162718772888},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.614464521408081},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.5952391624450684},{"id":"https://openalex.org/C164866538","wikidata":"https://www.wikidata.org/wiki/Q367351","display_name":"Cluster (spacecraft)","level":2,"score":0.5539928674697876},{"id":"https://openalex.org/C96250715","wikidata":"https://www.wikidata.org/wiki/Q965330","display_name":"Estimation","level":2,"score":0.529246985912323},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.34425872564315796},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.24334850907325745},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1264469027519226},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09678393602371216},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas62602.2024.10808655","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas62602.2024.10808655","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1605203071","https://openalex.org/W1944814515","https://openalex.org/W1968636796","https://openalex.org/W1973264045","https://openalex.org/W1984588379","https://openalex.org/W2017927472","https://openalex.org/W2034999260","https://openalex.org/W2076265641","https://openalex.org/W2087275089","https://openalex.org/W2125831674","https://openalex.org/W2127434816","https://openalex.org/W2134249452","https://openalex.org/W2154347669","https://openalex.org/W2160252016","https://openalex.org/W2162756981","https://openalex.org/W2178990935","https://openalex.org/W4232603692","https://openalex.org/W4236913175","https://openalex.org/W4237162529","https://openalex.org/W4246849871"],"related_works":["https://openalex.org/W2014709025","https://openalex.org/W2155019192","https://openalex.org/W3125341812","https://openalex.org/W1991674760","https://openalex.org/W1668171714","https://openalex.org/W2155297398","https://openalex.org/W4380607112","https://openalex.org/W2218294330","https://openalex.org/W1997278405","https://openalex.org/W2347989876"],"abstract_inverted_index":{"Interconnect":[0],"in":[1,10],"modern":[2],"VLSI":[3],"design":[4,47,61],"has":[5],"become":[6],"a":[7,70,79,85,99,131],"dominant":[8],"factor":[9],"circuit":[11],"timing.":[12],"Existing":[13],"buffer":[14,55,137],"insertion":[15,138],"approaches":[16],"suffer":[17],"from":[18],"the":[19,24,52,60,105,111,135,146,151],"scalability":[20],"issue":[21],"due":[22],"to":[23,33,63,103,123,134],"high":[25],"computational":[26],"complexity.":[27],"Repeatedly":[28],"buffering":[29,87,119],"billions":[30],"of":[31,54,150],"interconnects":[32],"meet":[34],"timing":[35,42,65],"specifications":[36],"is":[37,114,121],"not":[38],"affordable.":[39],"However,":[40],"previous":[41],"estimation":[43,73],"algorithms":[44],"at":[45],"early":[46],"stages":[48],"cannot":[49],"accurately":[50],"capture":[51],"effects":[53],"insertion,":[56],"which":[57],"may":[58],"increase":[59],"iterations":[62],"reach":[64],"closure.":[66],"This":[67],"paper":[68],"proposes":[69],"two-step":[71],"delay":[72],"method":[74],"for":[75],"buffered":[76,126],"interconnect,":[77],"combining":[78],"heuristic":[80],"Steiner":[81,96],"tree":[82,93,113],"construction":[83],"and":[84,148],"virtual":[86,118],"algorithm.":[88,139],"The":[89],"proposed":[90,122,152],"multi-level":[91],"cluster":[92],"constructs":[94],"rectilinear":[95],"trees":[97],"through":[98],"recursive":[100],"clustering":[101],"mechanism":[102],"enhance":[104],"accuracy":[106,147],"on":[107,142],"high-fanout":[108],"nets.":[109],"After":[110],"routing":[112],"determined,":[115],"an":[116],"equation-based":[117],"algorithm":[120],"efficiently":[124],"estimate":[125],"interconnect":[127],"delays":[128],"while":[129],"keeping":[130],"similar":[132],"quality":[133],"golden":[136],"Experimental":[140],"results":[141],"industrial":[143],"cases":[144],"demonstrate":[145],"efficiency":[149],"approach.":[153]},"counts_by_year":[],"updated_date":"2025-12-19T19:40:27.379048","created_date":"2025-10-10T00:00:00"}