{"id":"https://openalex.org/W4210298702","doi":"https://doi.org/10.1109/apccas51387.2021.9687757","title":"An Approximate Adder with Reduced Error and Optimized Design Metrics","display_name":"An Approximate Adder with Reduced Error and Optimized Design Metrics","publication_year":2021,"publication_date":"2021-11-22","ids":{"openalex":"https://openalex.org/W4210298702","doi":"https://doi.org/10.1109/apccas51387.2021.9687757"},"language":"en","primary_location":{"id":"doi:10.1109/apccas51387.2021.9687757","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas51387.2021.9687757","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5008761321","display_name":"Padmanabhan Balasubramanian","orcid":"https://orcid.org/0000-0001-9412-4773"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":true,"raw_author_name":"Padmanabhan Balasubramanian","raw_affiliation_strings":["School of Computer Science and Engineering, Nanyang Technological University,Singapore,639798"],"affiliations":[{"raw_affiliation_string":"School of Computer Science and Engineering, Nanyang Technological University,Singapore,639798","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049854582","display_name":"Raunaq Nayar","orcid":"https://orcid.org/0000-0003-3109-8197"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Raunaq Nayar","raw_affiliation_strings":["School of Computer Science and Engineering, Nanyang Technological University,Singapore,639798"],"affiliations":[{"raw_affiliation_string":"School of Computer Science and Engineering, Nanyang Technological University,Singapore,639798","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059218594","display_name":"Douglas L. Maskell","orcid":"https://orcid.org/0000-0002-6588-4762"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Douglas Maskell","raw_affiliation_strings":["School of Computer Science and Engineering, Nanyang Technological University,Singapore,639798"],"affiliations":[{"raw_affiliation_string":"School of Computer Science and Engineering, Nanyang Technological University,Singapore,639798","institution_ids":["https://openalex.org/I172675005"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5008761321"],"corresponding_institution_ids":["https://openalex.org/I172675005"],"apc_list":null,"apc_paid":null,"fwci":0.711,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.70850212,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"21","last_page":"24"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8835161924362183},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6359460353851318},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3897576928138733},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3643531799316406},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3578883409500122},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3339591324329376},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.19145473837852478},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13256752490997314},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10414361953735352}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8835161924362183},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6359460353851318},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3897576928138733},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3643531799316406},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3578883409500122},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3339591324329376},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.19145473837852478},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13256752490997314},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10414361953735352},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas51387.2021.9687757","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas51387.2021.9687757","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.7200000286102295}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1580963329","https://openalex.org/W2005865544","https://openalex.org/W2030922317","https://openalex.org/W2079986413","https://openalex.org/W2133665775","https://openalex.org/W2135089667","https://openalex.org/W2280900335","https://openalex.org/W2801205959","https://openalex.org/W2919795555","https://openalex.org/W2967210860","https://openalex.org/W2982216783","https://openalex.org/W3011299928","https://openalex.org/W3048414096","https://openalex.org/W3071517735","https://openalex.org/W3116186505"],"related_works":["https://openalex.org/W4390550886","https://openalex.org/W3217463396","https://openalex.org/W2790557758","https://openalex.org/W2516396101","https://openalex.org/W3204929712","https://openalex.org/W4295102875","https://openalex.org/W2300671402","https://openalex.org/W2015457513","https://openalex.org/W2013839957","https://openalex.org/W3196607417"],"abstract_inverted_index":{"We":[0,35,53,77,96,124],"present":[1],"a":[2,37,48,131,163,189],"new":[3],"approximate":[4,15,23,75,85,104],"adder":[5,16,24,102,161],"with":[6,148],"reduced":[7],"error":[8,56,62,66,72],"and":[9,26,68,84,90,103,119,181,184,192,206],"optimized":[10],"design":[11,80,155],"metrics.":[12],"The":[13],"proposed":[14,128],"is":[17,27,135,146],"derived":[18],"by":[19,111],"modifying":[20],"an":[21,44,107,213],"existing":[22],"HERLOA":[25,30,41],"called":[28,64],"modified":[29],"or":[31],"M-HERLOA":[32,46,129,149],"in":[33,154,170,176,196,202,209],"short.":[34],"considered":[36],"systematic":[38],"modification":[39],"of":[40,73,82,100],"to":[42,116,137,158],"derive":[43],"optimum":[45],"for":[47,106,162,188,212],"digital":[49,132],"image":[50,108,133,139],"processing":[51,109],"application.":[52],"calculated":[54],"popular":[55],"parameters":[57],"such":[58],"as":[59],"mean":[60,65,70],"absolute":[61],"(also":[63],"distance)":[67],"root":[69],"square":[71],"the":[74,79,98,113,127,138,142,159],"adders.":[76],"estimated":[78],"metrics":[81,156],"accurate":[83,101,143,160],"adders":[86,105],"based":[87],"on":[88],"FPGA":[89,190],"ASIC":[91,214],"(standard":[92],"cell":[93],"based)":[94],"implementations.":[95],"compare":[97],"performance":[99],"application":[110],"estimating":[112],"peak":[114],"signal":[115],"noise":[117],"ratio":[118],"structural":[120],"similarity":[121],"index":[122],"metric.":[123],"find":[125],"that":[126,134],"reconstructs":[130],"similar":[136],"reconstructed":[140],"using":[141],"adder.":[144],"This":[145],"achieved":[147],"simultaneously":[150],"enabling":[151],"following":[152],"optimizations":[153],"compared":[157],"32":[164],"bit":[165],"addition:":[166],"(i)":[167],"9.5%":[168],"reduction":[169,175,195,201,208],"minimum":[171],"clock":[172],"period,":[173],"9.1%":[174],"total":[177],"on-chip":[178],"power":[179,204],"consumption,":[180],"7":[182],"LUTs":[183],"18":[185],"flip-flops":[186],"less":[187],"implementation,":[191],"(ii)":[193],"18%":[194],"critical":[197],"path":[198],"delay,":[199],"26.7%":[200],"average":[203],"dissipation,":[205],"23.1%":[207],"silicon":[210],"area":[211],"type":[215],"implementation.":[216]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":10},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1}],"updated_date":"2026-04-02T15:55:50.835912","created_date":"2025-10-10T00:00:00"}