{"id":"https://openalex.org/W4210623756","doi":"https://doi.org/10.1109/apccas51387.2021.9687695","title":"A 20 GHz 8-bit All-N-Transistor Logic CLA Using 16-nm FinFET Technology","display_name":"A 20 GHz 8-bit All-N-Transistor Logic CLA Using 16-nm FinFET Technology","publication_year":2021,"publication_date":"2021-11-22","ids":{"openalex":"https://openalex.org/W4210623756","doi":"https://doi.org/10.1109/apccas51387.2021.9687695"},"language":"en","primary_location":{"id":"doi:10.1109/apccas51387.2021.9687695","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas51387.2021.9687695","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070314228","display_name":"Tzung-Je Lee","orcid":"https://orcid.org/0000-0001-6870-7406"},"institutions":[{"id":"https://openalex.org/I142974352","display_name":"National Sun Yat-sen University","ror":"https://ror.org/00mjawt10","country_code":"TW","type":"education","lineage":["https://openalex.org/I142974352"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Tzung-Je Lee","raw_affiliation_strings":["National Sun Yat-Sen University,Department of Electrical Engineering,Kaohsiung,Taiwan,80424"],"affiliations":[{"raw_affiliation_string":"National Sun Yat-Sen University,Department of Electrical Engineering,Kaohsiung,Taiwan,80424","institution_ids":["https://openalex.org/I142974352"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5114035129","display_name":"Wen-Shou Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I142974352","display_name":"National Sun Yat-sen University","ror":"https://ror.org/00mjawt10","country_code":"TW","type":"education","lineage":["https://openalex.org/I142974352"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Wen-Shou Yang","raw_affiliation_strings":["National Sun Yat-Sen University,Department of Electrical Engineering,Kaohsiung,Taiwan,80424"],"affiliations":[{"raw_affiliation_string":"National Sun Yat-Sen University,Department of Electrical Engineering,Kaohsiung,Taiwan,80424","institution_ids":["https://openalex.org/I142974352"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077220045","display_name":"Chua\u2010Chin Wang","orcid":"https://orcid.org/0000-0002-2426-2879"},"institutions":[{"id":"https://openalex.org/I142974352","display_name":"National Sun Yat-sen University","ror":"https://ror.org/00mjawt10","country_code":"TW","type":"education","lineage":["https://openalex.org/I142974352"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chua-Chin Wang","raw_affiliation_strings":["National Sun Yat-Sen University,Department of Electrical Engineering,Kaohsiung,Taiwan,80424"],"affiliations":[{"raw_affiliation_string":"National Sun Yat-Sen University,Department of Electrical Engineering,Kaohsiung,Taiwan,80424","institution_ids":["https://openalex.org/I142974352"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5070314228"],"corresponding_institution_ids":["https://openalex.org/I142974352"],"apc_list":null,"apc_paid":null,"fwci":0.4011,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.61989951,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.8555512428283691},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.8283962607383728},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5472270846366882},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5399870872497559},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5150501728057861},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.5081057548522949},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5042604207992554},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.49786949157714844},{"id":"https://openalex.org/keywords/power\u2013delay-product","display_name":"Power\u2013delay product","score":0.465798944234848},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.4475657045841217},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.4366961717605591},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.42747771739959717},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.2641925811767578},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2435227632522583},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.15812230110168457}],"concepts":[{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.8555512428283691},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.8283962607383728},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5472270846366882},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5399870872497559},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5150501728057861},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.5081057548522949},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5042604207992554},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.49786949157714844},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.465798944234848},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.4475657045841217},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.4366961717605591},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.42747771739959717},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.2641925811767578},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2435227632522583},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.15812230110168457},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas51387.2021.9687695","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas51387.2021.9687695","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8399999737739563}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1597620877","https://openalex.org/W1643678676","https://openalex.org/W2021081671","https://openalex.org/W2046103068","https://openalex.org/W2080259168","https://openalex.org/W2140077908","https://openalex.org/W2140958423","https://openalex.org/W2161994206","https://openalex.org/W2803057706","https://openalex.org/W2903539032","https://openalex.org/W3010273802","https://openalex.org/W3011688954","https://openalex.org/W3118472427","https://openalex.org/W4229831601"],"related_works":["https://openalex.org/W4386261925","https://openalex.org/W2082944690","https://openalex.org/W2263373136","https://openalex.org/W1914349328","https://openalex.org/W2104885411","https://openalex.org/W2023334077","https://openalex.org/W2005494397","https://openalex.org/W2478796561","https://openalex.org/W91469557","https://openalex.org/W4245780952"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,92,117],"20":[4,118,130],"GHz":[5,131],"8-bit":[6,66],"carry-lookahead":[7],"adder":[8],"(CLA)":[9],"using":[10,15],"all-N-transistor":[11],"(ANT)":[12],"logic.":[13],"By":[14],"the":[16,31,40,47,50,54,57,61,65,74,80,110],"proposed":[17,87],"ANT":[18],"logic,":[19],"an":[20],"auxiliary":[21],"current":[22],"path":[23,63],"through":[24],"NMOS":[25],"transistor":[26],"is":[27,37,43,68,89,101,113,125],"provided":[28],"such":[29],"that":[30],"speed":[32,48],"limitation":[33],"caused":[34],"by":[35,78],"PMOS":[36],"avoided.":[38],"Besides,":[39],"FinFET":[41,84,96],"device":[42],"used":[44],"to":[45,72],"improve":[46,73],"with":[49,91],"enhanced":[51],"mobility.":[52],"Moreover,":[53],"analysis":[55],"of":[56,64],"delay":[58,111],"time":[59,112],"for":[60],"critical":[62],"CLA":[67],"also":[69],"carried":[70],"out":[71],"PDP":[75,124],"(Power-Delay":[76],"Product)":[77],"considering":[79],"parasitic":[81],"R-C":[82],"in":[83],"devices.":[85],"The":[86,98,122],"design":[88],"implemented":[90],"typical":[93],"16":[94],"nm":[95],"process.":[97],"core":[99],"area":[100],"<tex>$206.403":[102],"\\times":[103],"152.506\\":[104],"\\mu\\mathrm{m}^{2}$</tex>.":[105],"Based":[106],"on":[107],"post-layout":[108],"simulations,":[109],"931":[114],"ps":[115],"at":[116,129],"pF":[119],"capacitive":[120],"load.":[121],"simulated":[123],"only":[126],"21.67":[127],"pW":[128],"clock":[132],"rate.":[133]},"counts_by_year":[{"year":2024,"cited_by_count":3},{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}