{"id":"https://openalex.org/W2908736411","doi":"https://doi.org/10.1109/apccas.2018.8605644","title":"A Novel Compiler for Regular Expression Matching Engine Construction","display_name":"A Novel Compiler for Regular Expression Matching Engine Construction","publication_year":2018,"publication_date":"2018-10-01","ids":{"openalex":"https://openalex.org/W2908736411","doi":"https://doi.org/10.1109/apccas.2018.8605644","mag":"2908736411"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2018.8605644","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2018.8605644","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075943675","display_name":"Xin Jin","orcid":"https://orcid.org/0000-0002-0142-6076"},"institutions":[{"id":"https://openalex.org/I881766915","display_name":"Nanjing University","ror":"https://ror.org/01rxvg760","country_code":"CN","type":"education","lineage":["https://openalex.org/I881766915"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Xin Jin","raw_affiliation_strings":["School of Electronic Science and Engineering, Nanjing University, P.R. China"],"affiliations":[{"raw_affiliation_string":"School of Electronic Science and Engineering, Nanjing University, P.R. China","institution_ids":["https://openalex.org/I881766915"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019940239","display_name":"Jun Lin","orcid":"https://orcid.org/0000-0003-2760-4333"},"institutions":[{"id":"https://openalex.org/I881766915","display_name":"Nanjing University","ror":"https://ror.org/01rxvg760","country_code":"CN","type":"education","lineage":["https://openalex.org/I881766915"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jun Lin","raw_affiliation_strings":["School of Electronic Science and Engineering, Nanjing University, P.R. China"],"affiliations":[{"raw_affiliation_string":"School of Electronic Science and Engineering, Nanjing University, P.R. China","institution_ids":["https://openalex.org/I881766915"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100696999","display_name":"Zhongfeng Wang","orcid":"https://orcid.org/0000-0002-7227-4786"},"institutions":[{"id":"https://openalex.org/I881766915","display_name":"Nanjing University","ror":"https://ror.org/01rxvg760","country_code":"CN","type":"education","lineage":["https://openalex.org/I881766915"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhongfeng Wang","raw_affiliation_strings":["School of Electronic Science and Engineering, Nanjing University, P.R. China"],"affiliations":[{"raw_affiliation_string":"School of Electronic Science and Engineering, Nanjing University, P.R. China","institution_ids":["https://openalex.org/I881766915"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5075943675"],"corresponding_institution_ids":["https://openalex.org/I881766915"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.18174041,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"3","issue":null,"first_page":"251","last_page":"256"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11567","display_name":"semigroups and automata theory","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8564046621322632},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.8400980234146118},{"id":"https://openalex.org/keywords/regular-expression","display_name":"Regular expression","score":0.7723930478096008},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.5632665157318115},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5538333654403687},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.47131210565567017},{"id":"https://openalex.org/keywords/pattern-matching","display_name":"Pattern matching","score":0.4335317611694336},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4133453369140625},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2659100890159607}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8564046621322632},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.8400980234146118},{"id":"https://openalex.org/C121329065","wikidata":"https://www.wikidata.org/wiki/Q185612","display_name":"Regular expression","level":2,"score":0.7723930478096008},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.5632665157318115},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5538333654403687},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.47131210565567017},{"id":"https://openalex.org/C68859911","wikidata":"https://www.wikidata.org/wiki/Q1503724","display_name":"Pattern matching","level":2,"score":0.4335317611694336},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4133453369140625},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2659100890159607}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2018.8605644","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2018.8605644","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1707172707","https://openalex.org/W1987557508","https://openalex.org/W2054801208","https://openalex.org/W2067845746","https://openalex.org/W2072607050","https://openalex.org/W2077224377","https://openalex.org/W2105956753","https://openalex.org/W2113425091","https://openalex.org/W2124183294","https://openalex.org/W2129414328","https://openalex.org/W2141607151","https://openalex.org/W2170523504","https://openalex.org/W2393727648","https://openalex.org/W6637452973"],"related_works":["https://openalex.org/W2387264083","https://openalex.org/W2604877941","https://openalex.org/W2390885485","https://openalex.org/W2114177167","https://openalex.org/W1774017438","https://openalex.org/W2123199373","https://openalex.org/W4246925412","https://openalex.org/W2083577879","https://openalex.org/W4205780093","https://openalex.org/W2052853109"],"abstract_inverted_index":{"Using":[0],"regular":[1,25,28,62,77,132,164],"expressions":[2,29,78,165],"in":[3,27,98,166,187],"intrusion":[4],"detection":[5],"systems":[6],"(IDS)":[7],"to":[8,41,47,105,127],"represent":[9],"some":[10],"dangerous":[11],"payload":[12],"contents":[13],"is":[14,39,45],"a":[15,32,49,56,143,146,190],"more":[16,160],"efficient":[17],"way":[18],"than":[19,161,168],"using":[20,82],"invariant":[21],"patterns.":[22],"For":[23],"each":[24],"expression":[26,63],"rules":[30],"set":[31],"unique":[33],"Nondeterministic":[34],"Finite":[35],"Automaton":[36],"(NFA)":[37],"structure":[38,126],"needed":[40],"be":[42],"converted.":[43],"It":[44],"crucial":[46],"implement":[48],"fast":[50],"NFA":[51],"construction.":[52],"This":[53],"paper":[54],"presents":[55],"novel":[57],"method":[58,109],"for":[59,74],"compiling":[60],"large-scale":[61],"matching":[64],"engine":[65,134],"(REME)":[66,135],"on":[67,90],"FPGA.":[68],"We":[69],"build":[70,128],"an":[71,178],"intelligent":[72],"compiler":[73,119,157,176],"automatic":[75],"converting":[76,108,112,173],"into":[79],"register-transfer-level":[80],"(RTL)":[81],"Verilog":[83,188],"language,":[84],"utilizing":[85],"only":[86],"logic":[87],"slice":[88],"available":[89],"FPGA":[91],"because":[92],"of":[93,101,192],"the":[94,99,106,111,115,118,123,129,139,172,175,193],"simple":[95],"architecture":[96],"used":[97],"back-end":[100],"our":[102,156],"compiler.":[103],"Due":[104],"independent":[107],"between":[110],"flow":[113],"and":[114,152,182],"block":[116],"structure,":[117],"can":[120,137,158],"easily":[121],"change":[122],"single":[124],"pattern":[125],"most":[130],"advanced":[131],"expression-matching":[133],"which":[136],"fit":[138],"realistic":[140],"demand.":[141],"On":[142],"PC":[144],"with":[145],"3.3":[147],"GHz":[148],"Intel":[149],"i5-4590":[150],"processor":[151],"4":[153],"GB":[154],"memory,":[155],"convert":[159],"one":[162],"thousand":[163],"less":[167],"15":[169],"seconds.":[170],"During":[171],"flow,":[174],"provides":[177],"arbitrary":[179],"match":[180],"string":[181],"corresponding":[183],"test":[184],"bench":[185],"file":[186],"as":[189],"part":[191],"final":[194],"output":[195],"result.":[196]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}