{"id":"https://openalex.org/W2908723661","doi":"https://doi.org/10.1109/apccas.2018.8605632","title":"Analytical Modeling of Process Variability in Subthreshold Regime for Ultra Low Power Applications","display_name":"Analytical Modeling of Process Variability in Subthreshold Regime for Ultra Low Power Applications","publication_year":2018,"publication_date":"2018-10-01","ids":{"openalex":"https://openalex.org/W2908723661","doi":"https://doi.org/10.1109/apccas.2018.8605632","mag":"2908723661"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2018.8605632","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2018.8605632","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5045732047","display_name":"M R Anala","orcid":null},"institutions":[{"id":"https://openalex.org/I53465836","display_name":"Bangalore University","ror":"https://ror.org/050j2vm64","country_code":"IN","type":"education","lineage":["https://openalex.org/I53465836"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Anala M.","raw_affiliation_strings":["Bangalore University, Bangalore, Karnataka, IN"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Bangalore University, Bangalore, Karnataka, IN","institution_ids":["https://openalex.org/I53465836"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108401813","display_name":"B. P. Harish","orcid":null},"institutions":[{"id":"https://openalex.org/I53465836","display_name":"Bangalore University","ror":"https://ror.org/050j2vm64","country_code":"IN","type":"education","lineage":["https://openalex.org/I53465836"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"B.P. Harish","raw_affiliation_strings":["Department of Electronics & Communication Engineering University Visvesvaraya College of Engineering, Bangalore University, Bangalore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics & Communication Engineering University Visvesvaraya College of Engineering, Bangalore University, Bangalore, India","institution_ids":["https://openalex.org/I53465836"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I53465836"],"apc_list":null,"apc_paid":null,"fwci":0.3928,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.65523474,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"257","last_page":"260"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/subthreshold-conduction","display_name":"Subthreshold conduction","score":0.8123859167098999},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.6796092987060547},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5807951092720032},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5478744506835938},{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.533647358417511},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5028061866760254},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4819778800010681},{"id":"https://openalex.org/keywords/threshold-voltage","display_name":"Threshold voltage","score":0.4747332036495209},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.45376837253570557},{"id":"https://openalex.org/keywords/semiconductor-device-modeling","display_name":"Semiconductor device modeling","score":0.4217895269393921},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.25352412462234497},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2533385753631592},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.241070955991745},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22810950875282288},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1880359649658203},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.15642651915550232},{"id":"https://openalex.org/keywords/statistics","display_name":"Statistics","score":0.08884268999099731}],"concepts":[{"id":"https://openalex.org/C156465305","wikidata":"https://www.wikidata.org/wiki/Q1658601","display_name":"Subthreshold conduction","level":4,"score":0.8123859167098999},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.6796092987060547},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5807951092720032},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5478744506835938},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.533647358417511},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5028061866760254},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4819778800010681},{"id":"https://openalex.org/C195370968","wikidata":"https://www.wikidata.org/wiki/Q1754002","display_name":"Threshold voltage","level":4,"score":0.4747332036495209},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.45376837253570557},{"id":"https://openalex.org/C4775677","wikidata":"https://www.wikidata.org/wiki/Q7449393","display_name":"Semiconductor device modeling","level":3,"score":0.4217895269393921},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.25352412462234497},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2533385753631592},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.241070955991745},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22810950875282288},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1880359649658203},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.15642651915550232},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.08884268999099731}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2018.8605632","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2018.8605632","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.7300000190734863,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1538618611","https://openalex.org/W1661368752","https://openalex.org/W1967665660","https://openalex.org/W1973284201","https://openalex.org/W1985235598","https://openalex.org/W1997782294","https://openalex.org/W2033443176","https://openalex.org/W2091881407","https://openalex.org/W2099457706","https://openalex.org/W2111372718","https://openalex.org/W2115224472","https://openalex.org/W2153299515","https://openalex.org/W2157982046","https://openalex.org/W2197932458","https://openalex.org/W2552587452","https://openalex.org/W3146163470","https://openalex.org/W4210341450","https://openalex.org/W4239145761","https://openalex.org/W4285719527","https://openalex.org/W6632160290","https://openalex.org/W6643673173","https://openalex.org/W6729835690"],"related_works":["https://openalex.org/W2162700382","https://openalex.org/W2009852498","https://openalex.org/W1991521745","https://openalex.org/W3004587385","https://openalex.org/W4220771873","https://openalex.org/W2786811717","https://openalex.org/W2069364674","https://openalex.org/W2062767191","https://openalex.org/W4231458110","https://openalex.org/W2109147260"],"abstract_inverted_index":{"Performance":[0],"variations":[1,34,161],"induced":[2],"by":[3,197],"increasing":[4],"process":[5,9,78,101,116,286],"variability":[6,27,102,117,121,145,154,184,250,269],"in":[7,76,82,122,162,174,185,220,251,272,282],"advanced":[8,77],"nodes":[10,79],"have":[11],"become":[12],"a":[13,55],"major":[14],"barrier":[15],"to":[16,20,65,86,96,104,148,156],"performance":[17,37,67],"enhancements":[18],"due":[19],"device":[21,140,169],"scaling.":[22],"The":[23,120,183,225,262],"growing":[24],"impact":[25],"of":[26,71,73,100,108,115,138,160,167,191,234,266,279,285],"on":[28,170,205],"CMOS":[29,193],"devices":[30],"manifests":[31],"as":[32,40,54,143],"large":[33],"among":[35],"all":[36],"metrics":[38,75],"such":[39],"delay,":[41],"power":[42,61],"dissipation,":[43],"reliability":[44],"and":[45,103,112,130,164,187,210,241,256,264],"yield.":[46],"Further,":[47],"the":[48,98,106,139,158,168,175,206,211,267,283],"subthreshold":[49,83,176],"circuit":[50,87,109,171,280],"design":[51,88,281],"is":[52,80,118,146,181,195,213,230],"emerging":[53],"potential":[56],"solution":[57],"for":[58,236,243,248],"ultra":[59],"low":[60,64],"applications":[62],"with":[63,178],"moderate":[66],"requirements.":[68],"High":[69],"levels":[70],"unpredictability":[72],"key":[74],"accentuated":[81],"regime,":[84,177],"leading":[85],"becoming":[89],"that":[90],"much":[91],"more":[92],"challenging.":[93],"In":[94],"order":[95],"mitigate":[97],"risk":[99],"enhance":[105],"predictability":[107,278],"design,":[110],"accurate":[111],"reliable":[113],"modeling":[114],"critical.":[119],"threshold":[123],"voltage":[124],"(V":[125],"<inf":[126,134,238,245,253,258],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[127,135,239,246,254,259],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">th</inf>":[128,255],")":[129,137],"gate":[131],"length":[132],"(L":[133],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">g</inf>":[136,260],"are":[141],"considered,":[142],"their":[144],"reported":[147],"be":[149],"dominant.":[150],"An":[151],"analytical":[152,208],"delay":[153,172,190,228,268,274],"model":[155,209,212,226,270],"evaluate":[157],"effect":[159],"electrical":[163],"geometry":[165],"parameters":[166],"estimation":[173],"DIBL":[179],"considerations,":[180],"proposed.":[182],"rising":[186],"falling":[188],"edge":[189],"static":[192],"inverter":[194],"characterized":[196],"using":[198],"an":[199,232],"extensive":[200],"Monte":[201,216],"Carlo":[202,217],"analysis":[203],"based":[204],"proposed":[207],"validated":[214],"against":[215],"SPICE":[218],"simulations":[219],"32":[221],"nm":[222],"PTM":[223],"technology.":[224],"predicted":[227],"mean":[229],"within":[231],"error":[233],"1.97%":[235],"\u03c4":[237,244],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">pHL</inf>":[240],"\u22122.70%":[242],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">pLH</inf>":[247],"20%":[249],"V":[252],"L":[257],"each.":[261],"simplicity":[263],"accuracy":[265],"resulting":[271],"tighter":[273],"distributions":[275],"demonstrates":[276],"better":[277],"presence":[284],"variations.":[287]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}
