{"id":"https://openalex.org/W2910782178","doi":"https://doi.org/10.1109/apccas.2018.8605606","title":"Benchmark of RRAM based Architectures for Dot-Product Computation","display_name":"Benchmark of RRAM based Architectures for Dot-Product Computation","publication_year":2018,"publication_date":"2018-10-01","ids":{"openalex":"https://openalex.org/W2910782178","doi":"https://doi.org/10.1109/apccas.2018.8605606","mag":"2910782178"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2018.8605606","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2018.8605606","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5076031530","display_name":"Xiaochen Peng","orcid":"https://orcid.org/0000-0001-6148-7711"},"institutions":[{"id":"https://openalex.org/I55732556","display_name":"Arizona State University","ror":"https://ror.org/03efmqc40","country_code":"US","type":"education","lineage":["https://openalex.org/I55732556"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiaochen Peng","raw_affiliation_strings":["School of Electrical, Computing and Energy Engineering, Arizona State University, Tempe, AZ"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical, Computing and Energy Engineering, Arizona State University, Tempe, AZ","institution_ids":["https://openalex.org/I55732556"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5054894631","display_name":"Shimeng Yu","orcid":"https://orcid.org/0000-0002-0068-3652"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shimeng Yu","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"378","last_page":"381"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12676","display_name":"Machine Learning and ELM","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.882453441619873},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7014247179031372},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6184582114219666},{"id":"https://openalex.org/keywords/xnor-gate","display_name":"XNOR gate","score":0.5050824284553528},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5042499303817749},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4918949604034424},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.440395712852478},{"id":"https://openalex.org/keywords/efficient-energy-use","display_name":"Efficient energy use","score":0.422486275434494},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.41841933131217957},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.4182947278022766},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3454183042049408},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3355979025363922},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.2226225733757019},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14941024780273438},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14878425002098083},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.140607088804245},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1324181854724884}],"concepts":[{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.882453441619873},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7014247179031372},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6184582114219666},{"id":"https://openalex.org/C57684291","wikidata":"https://www.wikidata.org/wiki/Q1336142","display_name":"XNOR gate","level":4,"score":0.5050824284553528},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5042499303817749},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4918949604034424},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.440395712852478},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.422486275434494},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.41841933131217957},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.4182947278022766},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3454183042049408},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3355979025363922},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2226225733757019},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14941024780273438},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14878425002098083},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.140607088804245},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1324181854724884},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2018.8605606","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2018.8605606","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8899999856948853}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1604973310","https://openalex.org/W2057055374","https://openalex.org/W2288519604","https://openalex.org/W2319920447","https://openalex.org/W2442974303","https://openalex.org/W2508602506","https://openalex.org/W2510331918","https://openalex.org/W2518281301","https://openalex.org/W2606722458","https://openalex.org/W2785141883","https://openalex.org/W2787759178","https://openalex.org/W2798554798","https://openalex.org/W2953212265","https://openalex.org/W4249616338","https://openalex.org/W6696589972"],"related_works":["https://openalex.org/W2108719777","https://openalex.org/W2910771446","https://openalex.org/W2966758645","https://openalex.org/W2559054477","https://openalex.org/W2122693377","https://openalex.org/W2532170798","https://openalex.org/W4320854861","https://openalex.org/W3048955117","https://openalex.org/W2166656370","https://openalex.org/W2993390155"],"abstract_inverted_index":{"Memory":[0],"array":[1],"architecture":[2,124],"based":[3,110],"on":[4,111],"emerging":[5],"non-volatile":[6],"memory":[7,41],"devices":[8],"have":[9,27],"been":[10],"proposed":[11],"for":[12,76],"on-chip":[13],"acceleration":[14],"of":[15,93,120],"dot-product":[16,91],"computation":[17,39],"in":[18,24,98],"neural":[19],"networks.":[20],"As":[21],"recent":[22],"advances":[23],"machine":[25],"learning":[26],"shown":[28],"that":[29],"precision":[30],"reduction":[31],"is":[32,44],"a":[33,56,94],"useful":[34],"technique":[35],"to":[36,46,62,88,137],"reduce":[37],"the":[38,64,77,90,118,121,138],"and":[40,73,79,101,114,133,140],"storage,":[42],"it":[43],"desired":[45],"evaluate":[47],"their":[48],"hardware":[49],"cost.":[50],"In":[51],"this":[52],"paper,":[53],"we":[54],"use":[55],"circuit-level":[57,65],"macro":[58],"model,":[59],"i.e.":[60],"NeuroSim,":[61],"benchmark":[63],"performance":[66],"metrics,":[67],"such":[68],"as":[69],"chip":[70],"area,":[71],"latency,":[72],"dynamic":[74],"energy":[75],"XNOR-RRAM":[78,123],"conventional":[80,142],"8-bit":[81,143],"RRAM":[82,112,144],"architectures.":[83],"Both":[84],"architectures":[85,145],"are":[86,109],"implemented":[87],"process":[89],"operation":[92],"512\u00d7512":[95],"synaptic":[96],"matrix":[97],"sequential":[99,141],"row-by-row":[100],"parallel":[102,122,139],"read-out":[103],"fashion":[104],"separately.":[105],"The":[106],"simulation":[107],"results":[108],"models":[113],"32nm":[115],"CMOS":[116],"PDK,":[117],"energy-efficiency":[119],"could":[125],"achieve":[126],"311":[127],"TOPS/W,":[128],"showing":[129],"at":[130],"least":[131],"~15\u00d7":[132],"~621\u00d7":[134],"improvement":[135],"compared":[136],"respectively.":[146]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2020,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}