{"id":"https://openalex.org/W2575031633","doi":"https://doi.org/10.1109/apccas.2016.7804022","title":"Multiple-patterning lithography-aware routing for standard cell layout synthesis","display_name":"Multiple-patterning lithography-aware routing for standard cell layout synthesis","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W2575031633","doi":"https://doi.org/10.1109/apccas.2016.7804022","mag":"2575031633"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2016.7804022","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2016.7804022","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071820714","display_name":"Kuen-Wey Lin","orcid":"https://orcid.org/0009-0003-9029-4996"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Kuen-Wey Lin","raw_affiliation_strings":["Institute of Computer Science and Engineering, National Chiao Tung University, Hsin-Chu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Institute of Computer Science and Engineering, National Chiao Tung University, Hsin-Chu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034618339","display_name":"Yih-Lang Li","orcid":"https://orcid.org/0000-0002-6441-2392"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yih-Lang Li","raw_affiliation_strings":["Institute of Computer Science and Engineering, National Chiao Tung University, Hsin-Chu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Institute of Computer Science and Engineering, National Chiao Tung University, Hsin-Chu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109219585","display_name":"Rung\u2010Bin Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I99908691","display_name":"Yuan Ze University","ror":"https://ror.org/01fv1ds98","country_code":"TW","type":"education","lineage":["https://openalex.org/I99908691"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Rung-Bin Lin","raw_affiliation_strings":["Department of Computer Science and Engineering, Yuan Ze University, Taoyuan, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Yuan Ze University, Taoyuan, Taiwan","institution_ids":["https://openalex.org/I99908691"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5071820714"],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.15633875,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"534","last_page":"537"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-for-manufacturability","display_name":"Design for manufacturability","score":0.8579067587852478},{"id":"https://openalex.org/keywords/lithography","display_name":"Lithography","score":0.6930679678916931},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6673988103866577},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6546571850776672},{"id":"https://openalex.org/keywords/multiple-patterning","display_name":"Multiple patterning","score":0.6134156584739685},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.5847362279891968},{"id":"https://openalex.org/keywords/extreme-ultraviolet-lithography","display_name":"Extreme ultraviolet lithography","score":0.5739769339561462},{"id":"https://openalex.org/keywords/ic-layout-editor","display_name":"IC layout editor","score":0.5358191132545471},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.5321399569511414},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.49797964096069336},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.35912686586380005},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.32558274269104004},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2586938142776489},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.25244757533073425},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.2120538055896759},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.18355002999305725},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1815706491470337},{"id":"https://openalex.org/keywords/resist","display_name":"Resist","score":0.1721450388431549},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.14912652969360352},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.1369493305683136},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.12465998530387878},{"id":"https://openalex.org/keywords/nanotechnology","display_name":"Nanotechnology","score":0.1114727258682251},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.07273775339126587}],"concepts":[{"id":"https://openalex.org/C62064638","wikidata":"https://www.wikidata.org/wiki/Q553878","display_name":"Design for manufacturability","level":2,"score":0.8579067587852478},{"id":"https://openalex.org/C204223013","wikidata":"https://www.wikidata.org/wiki/Q133036","display_name":"Lithography","level":2,"score":0.6930679678916931},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6673988103866577},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6546571850776672},{"id":"https://openalex.org/C177409738","wikidata":"https://www.wikidata.org/wiki/Q1917460","display_name":"Multiple patterning","level":4,"score":0.6134156584739685},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.5847362279891968},{"id":"https://openalex.org/C162996421","wikidata":"https://www.wikidata.org/wiki/Q371965","display_name":"Extreme ultraviolet lithography","level":2,"score":0.5739769339561462},{"id":"https://openalex.org/C5546195","wikidata":"https://www.wikidata.org/wiki/Q5969842","display_name":"IC layout editor","level":5,"score":0.5358191132545471},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.5321399569511414},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.49797964096069336},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35912686586380005},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.32558274269104004},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2586938142776489},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.25244757533073425},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2120538055896759},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.18355002999305725},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1815706491470337},{"id":"https://openalex.org/C53524968","wikidata":"https://www.wikidata.org/wiki/Q7315582","display_name":"Resist","level":3,"score":0.1721450388431549},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.14912652969360352},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.1369493305683136},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.12465998530387878},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.1114727258682251},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.07273775339126587},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2016.7804022","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2016.7804022","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.44999998807907104,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1966149271","https://openalex.org/W1975619379","https://openalex.org/W1980519916","https://openalex.org/W1985269856","https://openalex.org/W1996055445","https://openalex.org/W2009815534","https://openalex.org/W2051394940","https://openalex.org/W2089790389","https://openalex.org/W2099280005","https://openalex.org/W2122848041","https://openalex.org/W2142968870","https://openalex.org/W2154270731","https://openalex.org/W2157910601","https://openalex.org/W2168344058","https://openalex.org/W2949126383","https://openalex.org/W3150055114","https://openalex.org/W4238726164","https://openalex.org/W6646746451","https://openalex.org/W6663391026"],"related_works":["https://openalex.org/W2388589331","https://openalex.org/W3146205511","https://openalex.org/W2357425846","https://openalex.org/W162881505","https://openalex.org/W2376028644","https://openalex.org/W2376726667","https://openalex.org/W2023781639","https://openalex.org/W2997716136","https://openalex.org/W2167755864","https://openalex.org/W2805222980"],"abstract_inverted_index":{"As":[0],"features":[1,54],"in":[2,36,55,103,125,155,191],"semiconductor":[3],"technology":[4,57],"become":[5],"extremely":[6],"scaled":[7],"down,":[8],"manufacturability":[9],"is":[10,49,165],"becoming":[11],"a":[12],"great":[13],"challenge.":[14],"Owing":[15],"to":[16,51,105,141],"the":[17,66,78,109,113,143,160,169,182],"delayed":[18],"adoption":[19],"of":[20,71,80,115,145,153,181],"new":[21],"lithographic":[22],"techniques,":[23],"such":[24],"as":[25],"extreme":[26],"ultraviolet":[27],"(EUV),":[28],"e-beam":[29],"direct-write":[30],"(EBDW),":[31],"and":[32,69,85,93,117,137,157],"directed":[33],"self-assembly":[34],"(DSA),":[35],"IC":[37],"volume":[38],"production,":[39],"double":[40],"patterning":[41,46],"lithography":[42,47,95],"(DPL)":[43],"or":[44],"multiple":[45],"(MPL)":[48],"used":[50],"print":[52],"critical":[53],"advanced":[56,192],"nodes.":[58],"DPL/MPL":[59,106,156],"imposes":[60],"many":[61],"restrictive":[62,170],"design":[63,79,139,171,189],"rules":[64,140,172,190],"on":[65,77,83,159],"mask":[67],"layout":[68,90,128,185],"most":[70],"previous":[72],"works":[73],"discuss":[74],"their":[75],"impact":[76],"interconnection,":[81],"especially":[82],"block":[84],"chip":[86],"level":[87],"routing.":[88],"The":[89,120,178],"decomposition":[91],"problem":[92,98,111,130,180],"multiple-patterning":[94],"aware":[96],"routing":[97,118,162],"have":[99],"been":[100],"widely":[101],"studied":[102],"relation":[104],"for":[107,167],"resolving":[108],"manufacturing":[110],"at":[112],"stages":[114],"post-routing":[116],"respectively.":[119],"same":[121],"challenges":[122],"also":[123,195],"happen":[124],"standard":[126,183],"cell":[127,184],"synthesis":[129,146,186],"that":[131,173],"has":[132],"another":[133],"limited":[134],"area":[135],"constraint":[136],"transistor":[138],"lower":[142],"feasibility":[144],"algorithms.":[147],"This":[148],"paper":[149],"provides":[150],"an":[151],"overview":[152],"issues":[154],"focus":[158],"gridless":[161],"model,":[163],"which":[164],"suitable":[166],"accommodating":[168],"are":[174],"imposed":[175],"by":[176],"DPL/MPL.":[177],"routability":[179],"under":[187],"conditional":[188],"nodes":[193],"will":[194],"be":[196],"addressed.":[197]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}