{"id":"https://openalex.org/W2578617547","doi":"https://doi.org/10.1109/apccas.2016.7804019","title":"Test access mechaism for stack test time reduction of 3-dimensional integrated circuit","display_name":"Test access mechaism for stack test time reduction of 3-dimensional integrated circuit","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W2578617547","doi":"https://doi.org/10.1109/apccas.2016.7804019","mag":"2578617547"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2016.7804019","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2016.7804019","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108630780","display_name":"Inhyuk Choi","orcid":null},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Inhyuk Choi","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036496809","display_name":"Hyunggoy Oh","orcid":null},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Hyunggoy Oh","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068528309","display_name":"Sungho Kang","orcid":"https://orcid.org/0000-0002-7093-2095"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Sungho Kang","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","institution_ids":["https://openalex.org/I193775966"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5108630780"],"corresponding_institution_ids":["https://openalex.org/I193775966"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.17096107,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"522","last_page":"525"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/stack","display_name":"Stack (abstract data type)","score":0.7283163666725159},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5946599841117859},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5808178782463074},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.5445043444633484},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.5095915794372559},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.45205163955688477},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.42784279584884644},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4086892306804657},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2538908123970032},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.180693119764328},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10159724950790405},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08680623769760132},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08014807105064392}],"concepts":[{"id":"https://openalex.org/C9395851","wikidata":"https://www.wikidata.org/wiki/Q177929","display_name":"Stack (abstract data type)","level":2,"score":0.7283163666725159},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5946599841117859},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5808178782463074},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.5445043444633484},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.5095915794372559},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.45205163955688477},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.42784279584884644},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4086892306804657},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2538908123970032},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.180693119764328},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10159724950790405},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08680623769760132},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08014807105064392},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2016.7804019","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2016.7804019","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2038476033","https://openalex.org/W2125982897","https://openalex.org/W2132155220","https://openalex.org/W2151243068","https://openalex.org/W2158277795","https://openalex.org/W2165642910","https://openalex.org/W4230995773","https://openalex.org/W4242912069"],"related_works":["https://openalex.org/W4285708951","https://openalex.org/W2147986372","https://openalex.org/W2786111245","https://openalex.org/W1979305473","https://openalex.org/W3009953521","https://openalex.org/W4234763172","https://openalex.org/W2992024382","https://openalex.org/W2125317684","https://openalex.org/W1588361197","https://openalex.org/W2006119235"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"the":[3,13,19,25,34,39,42,46,54,57,69,73],"reconfigurable":[4],"test":[5,15,22,35,43,49,60],"access":[6],"mechanism":[7],"(RTAM)":[8],"is":[9],"designed":[10],"based":[11],"on":[12],"emerging":[14],"standard":[16],"to":[17,37],"reduce":[18],"cumulative":[20,58],"stack":[21,48,59],"time":[23,61],"of":[24,41],"3-dimensional":[26],"integrated":[27],"circuit":[28],"(3-D":[29],"IC).":[30],"The":[31],"RTAM":[32,55],"enables":[33],"scheduling":[36],"reflect":[38],"variation":[40],"constraints":[44],"in":[45,72],"overall":[47],"phases.":[50],"Simulation":[51],"results":[52],"show":[53],"achieves":[56],"reduction":[62],"compared":[63],"with":[64],"a":[65],"non-reconfigurable":[66],"TAM":[67],"for":[68],"stacked":[70],"dies":[71],"3-D":[74],"IC.":[75]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
