{"id":"https://openalex.org/W2579728156","doi":"https://doi.org/10.1109/apccas.2016.7804003","title":"Memory access algorithm for low energy CPU/GPU heterogeneous systems with hybrid DRAM/NVM memory architecture","display_name":"Memory access algorithm for low energy CPU/GPU heterogeneous systems with hybrid DRAM/NVM memory architecture","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W2579728156","doi":"https://doi.org/10.1109/apccas.2016.7804003","mag":"2579728156"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2016.7804003","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2016.7804003","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021078032","display_name":"Tsai-Kan Chien","orcid":"https://orcid.org/0000-0002-9864-5768"},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Tsai-Kan Chien","raw_affiliation_strings":["Department of Electrical Engineering, National Cheng Kung University, Taiwan","ITRI, Electronic and Optoelectronic System Research Laboratories (EOSL), Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Taiwan","institution_ids":["https://openalex.org/I91807558"]},{"raw_affiliation_string":"ITRI, Electronic and Optoelectronic System Research Laboratories (EOSL), Taiwan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015109763","display_name":"Lih\u2010Yih Chiou","orcid":"https://orcid.org/0000-0002-4161-5787"},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Lih-Yih Chiou","raw_affiliation_strings":["Department of Electrical Engineering, National Cheng Kung University, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Taiwan","institution_ids":["https://openalex.org/I91807558"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022705832","display_name":"Chieh-Wen Cheng","orcid":null},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chieh-Wen Cheng","raw_affiliation_strings":["Department of Electrical Engineering, National Cheng Kung University, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Taiwan","institution_ids":["https://openalex.org/I91807558"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112150802","display_name":"Shyh-Shyuan Sheu","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Shyh-Shyuan Sheu","raw_affiliation_strings":["ITRI, Electronic and Optoelectronic System Research Laboratories (EOSL), Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ITRI, Electronic and Optoelectronic System Research Laboratories (EOSL), Taiwan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055475468","display_name":"Peihua Wang","orcid":"https://orcid.org/0000-0002-6665-3384"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Pei-Hua Wang","raw_affiliation_strings":["ITRI, Electronic and Optoelectronic System Research Laboratories (EOSL), Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ITRI, Electronic and Optoelectronic System Research Laboratories (EOSL), Taiwan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108417335","display_name":"Ming\u2010Jinn Tsai","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ming-Jinn Tsai","raw_affiliation_strings":["ITRI, Electronic and Optoelectronic System Research Laboratories (EOSL), Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ITRI, Electronic and Optoelectronic System Research Laboratories (EOSL), Taiwan","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5004605327","display_name":"Chih\u2010I Wu","orcid":"https://orcid.org/0000-0003-3613-7511"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chih-I Wu","raw_affiliation_strings":["ITRI, Electronic and Optoelectronic System Research Laboratories (EOSL), Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ITRI, Electronic and Optoelectronic System Research Laboratories (EOSL), Taiwan","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6409,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.70718835,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"2016","issue":null,"first_page":"461","last_page":"464"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9922999739646912,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.8799633979797363},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8222572803497314},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.6071045994758606},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5787222981452942},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5409082174301147},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.4530472755432129},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.4501150846481323},{"id":"https://openalex.org/keywords/energy-consumption","display_name":"Energy consumption","score":0.4415307343006134},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.4275645613670349},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.4268215000629425},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.4227152466773987},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4163115322589874},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.40010392665863037},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.36516591906547546},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3638002872467041},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.06947919726371765},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.06026384234428406}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.8799633979797363},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8222572803497314},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.6071045994758606},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5787222981452942},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5409082174301147},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.4530472755432129},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.4501150846481323},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.4415307343006134},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.4275645613670349},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.4268215000629425},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.4227152466773987},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4163115322589874},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.40010392665863037},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.36516591906547546},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3638002872467041},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.06947919726371765},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.06026384234428406},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/apccas.2016.7804003","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2016.7804003","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"},{"id":"mag:2753463690","is_oa":false,"landing_page_url":"http://jglobal.jst.go.jp/en/public/201702231261710705","pdf_url":null,"source":{"id":"https://openalex.org/S4306512817","display_name":"IEEE Conference Proceedings","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":"IEEE Conference Proceedings","raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.9100000262260437,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2018384083","https://openalex.org/W2067354926","https://openalex.org/W2076217257","https://openalex.org/W2153882937","https://openalex.org/W2166263440","https://openalex.org/W2168972302"],"related_works":["https://openalex.org/W2044064773","https://openalex.org/W2047684617","https://openalex.org/W1575240748","https://openalex.org/W2766165550","https://openalex.org/W2168550483","https://openalex.org/W1975698617","https://openalex.org/W2049272650","https://openalex.org/W2328679197","https://openalex.org/W2143690511","https://openalex.org/W2096506606"],"abstract_inverted_index":{"In":[0],"modern":[1],"mobile":[2],"devices,":[3],"the":[4,70,79],"CPU":[5],"and":[6,50],"GPU":[7],"can":[8,55],"jointly":[9],"access":[10,24,30,35,48],"one":[11],"shared":[12],"memory,":[13],"typically":[14],"consisting":[15,44],"of":[16,45,75,92],"only":[17],"DRAM,":[18],"by":[19,33,65,87],"using":[20],"heterogeneous":[21],"uniform":[22],"memory":[23,42,49,60],"(hUMA).":[25],"This":[26],"paper":[27],"proposes":[28],"an":[29],"algorithm,":[31],"migration":[32],"data":[34],"tendency":[36],"(MiDATE),":[37],"for":[38],"a":[39],"hybrid":[40,59],"main":[41],"architecture":[43],"resistive":[46],"random":[47],"DRAM.":[51],"The":[52],"MiDATE":[53,80],"algorithm":[54,81],"operate":[56],"on":[57,83],"this":[58],"architecture,":[61],"reducing":[62],"energy":[63],"consumption":[64],"83%":[66],"while":[67],"maintaining":[68],"approximately":[69],"same":[71],"speed":[72],"as":[73],"that":[74,91],"DRAM-only":[76],"systems.":[77],"Using":[78],"can,":[82],"average,":[84],"reduce":[85],"unfairness":[86],"36.5%":[88],"compared":[89],"with":[90],"conventional":[93],"hUMA":[94],"methods,":[95],"increasing":[96],"system":[97],"speed.":[98]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}