{"id":"https://openalex.org/W2579873736","doi":"https://doi.org/10.1109/apccas.2016.7803958","title":"A 2-clock-cycle Na\u00efve Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors","display_name":"A 2-clock-cycle Na\u00efve Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W2579873736","doi":"https://doi.org/10.1109/apccas.2016.7803958","mag":"2579873736"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2016.7803958","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2016.7803958","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024453014","display_name":"Itaru Hida","orcid":null},"institutions":[{"id":"https://openalex.org/I205349734","display_name":"Hokkaido University","ror":"https://ror.org/02e16g702","country_code":"JP","type":"education","lineage":["https://openalex.org/I205349734"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Itaru Hida","raw_affiliation_strings":["Graduate School of Information Science and Technology, Hokkaido University, Sapporo, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Information Science and Technology, Hokkaido University, Sapporo, Japan","institution_ids":["https://openalex.org/I205349734"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086631960","display_name":"Masayuki Ikebe","orcid":"https://orcid.org/0000-0002-6770-8260"},"institutions":[{"id":"https://openalex.org/I205349734","display_name":"Hokkaido University","ror":"https://ror.org/02e16g702","country_code":"JP","type":"education","lineage":["https://openalex.org/I205349734"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masayuki Ikebe","raw_affiliation_strings":["Graduate School of Information Science and Technology, Hokkaido University, Sapporo, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Information Science and Technology, Hokkaido University, Sapporo, Japan","institution_ids":["https://openalex.org/I205349734"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080170293","display_name":"Tetsuya Asai","orcid":"https://orcid.org/0000-0003-1158-9810"},"institutions":[{"id":"https://openalex.org/I205349734","display_name":"Hokkaido University","ror":"https://ror.org/02e16g702","country_code":"JP","type":"education","lineage":["https://openalex.org/I205349734"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Tetsuya Asai","raw_affiliation_strings":["Graduate School of Information Science and Technology, Hokkaido University, Sapporo, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Information Science and Technology, Hokkaido University, Sapporo, Japan","institution_ids":["https://openalex.org/I205349734"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5089388923","display_name":"Masato Motomura","orcid":"https://orcid.org/0000-0003-1543-1252"},"institutions":[{"id":"https://openalex.org/I205349734","display_name":"Hokkaido University","ror":"https://ror.org/02e16g702","country_code":"JP","type":"education","lineage":["https://openalex.org/I205349734"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masato Motomura","raw_affiliation_strings":["Graduate School of Information Science and Technology, Hokkaido University, Sapporo, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Information Science and Technology, Hokkaido University, Sapporo, Japan","institution_ids":["https://openalex.org/I205349734"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5024453014"],"corresponding_institution_ids":["https://openalex.org/I205349734"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.17331202,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"297","last_page":"300"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/branch-predictor","display_name":"Branch predictor","score":0.9489307403564453},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7232134342193604},{"id":"https://openalex.org/keywords/naive-bayes-classifier","display_name":"Naive Bayes classifier","score":0.5330399870872498},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.5069706439971924},{"id":"https://openalex.org/keywords/bayesian-probability","display_name":"Bayesian probability","score":0.5052338242530823},{"id":"https://openalex.org/keywords/classifier","display_name":"Classifier (UML)","score":0.5012338161468506},{"id":"https://openalex.org/keywords/bayes-theorem","display_name":"Bayes' theorem","score":0.4499439299106598},{"id":"https://openalex.org/keywords/extractor","display_name":"Extractor","score":0.43300861120224},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.42063796520233154},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.39745983481407166},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.3376843333244324},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3373069167137146},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.18524736166000366},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10487708449363708}],"concepts":[{"id":"https://openalex.org/C168522837","wikidata":"https://www.wikidata.org/wiki/Q679552","display_name":"Branch predictor","level":2,"score":0.9489307403564453},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7232134342193604},{"id":"https://openalex.org/C52001869","wikidata":"https://www.wikidata.org/wiki/Q812530","display_name":"Naive Bayes classifier","level":3,"score":0.5330399870872498},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.5069706439971924},{"id":"https://openalex.org/C107673813","wikidata":"https://www.wikidata.org/wiki/Q812534","display_name":"Bayesian probability","level":2,"score":0.5052338242530823},{"id":"https://openalex.org/C95623464","wikidata":"https://www.wikidata.org/wiki/Q1096149","display_name":"Classifier (UML)","level":2,"score":0.5012338161468506},{"id":"https://openalex.org/C207201462","wikidata":"https://www.wikidata.org/wiki/Q182505","display_name":"Bayes' theorem","level":3,"score":0.4499439299106598},{"id":"https://openalex.org/C117978034","wikidata":"https://www.wikidata.org/wiki/Q5422192","display_name":"Extractor","level":2,"score":0.43300861120224},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.42063796520233154},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.39745983481407166},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.3376843333244324},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3373069167137146},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.18524736166000366},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10487708449363708},{"id":"https://openalex.org/C21880701","wikidata":"https://www.wikidata.org/wiki/Q2144042","display_name":"Process engineering","level":1,"score":0.0},{"id":"https://openalex.org/C12267149","wikidata":"https://www.wikidata.org/wiki/Q282453","display_name":"Support vector machine","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2016.7803958","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2016.7803958","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1686420892","https://openalex.org/W2091676564","https://openalex.org/W2116627071","https://openalex.org/W2122410182","https://openalex.org/W2156484396","https://openalex.org/W2551880474","https://openalex.org/W2623293810","https://openalex.org/W4232751114","https://openalex.org/W6677566587"],"related_works":["https://openalex.org/W2061007994","https://openalex.org/W2408643487","https://openalex.org/W2145546531","https://openalex.org/W4256090683","https://openalex.org/W1586172811","https://openalex.org/W2537862391","https://openalex.org/W2417174640","https://openalex.org/W2510306697","https://openalex.org/W4312333632","https://openalex.org/W4285149902"],"abstract_inverted_index":{"In":[0],"this":[1,79],"paper,":[2],"we":[3],"propose":[4],"a":[5,15],"Bayesian":[6,59],"branch-prediction":[7],"circuit":[8,35,49,67],"consisting":[9],"of":[10],"an":[11],"instruction-feature":[12],"extractor":[13],"and":[14,61,77],"na\u00efve":[16],"Bayes":[17],"classifier":[18,48],"(NBC).":[19],"Its":[20],"purpose":[21],"is":[22,36,50,78],"to":[23],"replace":[24],"conventional":[25,40],"branch":[26,42,69],"predictors":[27],"in":[28],"modern":[29],"pipelined":[30,85],"RISC":[31],"microprocessors.":[32,86],"The":[33],"proposed":[34,54],"based":[37],"on":[38,83],"the":[39,46,53,65],"neural":[41],"predictor":[43],"[1];":[44],"however,":[45],"linear":[47],"replaced":[51],"by":[52],"NBC":[55,66],"circuit.":[56],"Implementing":[57],"approximate":[58],"computation":[60],"its":[62],"highly-parallel":[63],"architectures,":[64],"completes":[68],"prediction":[70],"within":[71],"2":[72],"clock":[73],"cycles":[74],"per":[75],"instruction,":[76],"suitable":[80],"for":[81],"implementation":[82],"standard":[84]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}