{"id":"https://openalex.org/W2577320931","doi":"https://doi.org/10.1109/apccas.2016.7803936","title":"Optimization of area and power in multi-mode power gating scheme for static memory elements","display_name":"Optimization of area and power in multi-mode power gating scheme for static memory elements","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W2577320931","doi":"https://doi.org/10.1109/apccas.2016.7803936","mag":"2577320931"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2016.7803936","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2016.7803936","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101762761","display_name":"Xing Su","orcid":"https://orcid.org/0000-0002-8507-8039"},"institutions":[{"id":"https://openalex.org/I90610280","display_name":"South China University of Technology","ror":"https://ror.org/0530pts50","country_code":"CN","type":"education","lineage":["https://openalex.org/I90610280"]},{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["CN","JP"],"is_corresponding":true,"raw_author_name":"Xing Su","raw_affiliation_strings":["Graduate School of Information, Waseda University, Kitakyushu, Japan","School of Automation Science and Engineering, South China University of Technology, Guangzhou, China"],"affiliations":[{"raw_affiliation_string":"Graduate School of Information, Waseda University, Kitakyushu, Japan","institution_ids":["https://openalex.org/I150744194"]},{"raw_affiliation_string":"School of Automation Science and Engineering, South China University of Technology, Guangzhou, China","institution_ids":["https://openalex.org/I90610280"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103496033","display_name":"Shinji Kimura","orcid":null},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Shinji Kimura","raw_affiliation_strings":["Graduate School of Information, Waseda University, Kitakyushu, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Information, Waseda University, Kitakyushu, Japan","institution_ids":["https://openalex.org/I150744194"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5101762761"],"corresponding_institution_ids":["https://openalex.org/I150744194","https://openalex.org/I90610280"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.15809064,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"214","last_page":"217"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.8110966086387634},{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.7996618151664734},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.717416524887085},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5967434644699097},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5962910056114197},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.538453996181488},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5294047594070435},{"id":"https://openalex.org/keywords/leakage-power","display_name":"Leakage power","score":0.5257640480995178},{"id":"https://openalex.org/keywords/trimming","display_name":"Trimming","score":0.5096855163574219},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.5032791495323181},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.4495736360549927},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4165806174278259},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.40214699506759644},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.32796838879585266},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2961278259754181},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2460053265094757},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.19366762042045593},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.1818026304244995},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.17046794295310974}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.8110966086387634},{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.7996618151664734},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.717416524887085},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5967434644699097},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5962910056114197},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.538453996181488},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5294047594070435},{"id":"https://openalex.org/C2987719587","wikidata":"https://www.wikidata.org/wiki/Q1811428","display_name":"Leakage power","level":4,"score":0.5257640480995178},{"id":"https://openalex.org/C56951928","wikidata":"https://www.wikidata.org/wiki/Q3539213","display_name":"Trimming","level":2,"score":0.5096855163574219},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.5032791495323181},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.4495736360549927},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4165806174278259},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.40214699506759644},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.32796838879585266},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2961278259754181},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2460053265094757},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.19366762042045593},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.1818026304244995},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.17046794295310974},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2016.7803936","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2016.7803936","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.6200000047683716,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1505213511","https://openalex.org/W1965022152","https://openalex.org/W2109458212","https://openalex.org/W2110999128","https://openalex.org/W2124210802","https://openalex.org/W2134575798","https://openalex.org/W2150291080","https://openalex.org/W2316587969","https://openalex.org/W4240752277","https://openalex.org/W4253202538","https://openalex.org/W6676534250","https://openalex.org/W6678477870"],"related_works":["https://openalex.org/W2004834197","https://openalex.org/W2404323568","https://openalex.org/W4378175625","https://openalex.org/W2952738319","https://openalex.org/W1970386983","https://openalex.org/W2980874615","https://openalex.org/W2025620052","https://openalex.org/W4255392205","https://openalex.org/W3005731895","https://openalex.org/W2143954265"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3],"optimization":[4],"method":[5],"of":[6,49,77,92,126,129],"area":[7,35,63,75],"and":[8,37,65,113],"power":[9,17,67,102,120],"for":[10],"static":[11],"memory":[12],"elements":[13],"by":[14,105,114],"using":[15],"multi-mode":[16],"gating":[18,121],"(MMPG)":[19],"scheme.":[20,122],"A":[21],"2-transistor":[22],"MMPG":[23,112],"scheme":[24],"replaces":[25],"the":[26,47,54,74,80,98,124],"usual":[27,95,111],"5-transistor":[28],"one":[29],"to":[30,45,87,90,108,117],"effectively":[31],"reduce":[32,62],"on":[33],"chip":[34],"overhead":[36,64,76],"leakage":[38,66,101],"power,":[39],"simultaneously":[40],"combining":[41],"trimming":[42],"circuits":[43],"(TC)":[44],"guarantee":[46],"safety":[48],"data":[50],"retention.":[51],"When":[52],"applying":[53],"proposed":[55,81,132],"approach":[56,82,133],"into":[57],"clean/dirty-cache":[58],"(CD-cache),":[59],"we":[60],"can":[61,134],"consumption.":[68],"The":[69],"simulation":[70],"results":[71],"show":[72],"that":[73,91],"SRAM":[78,93,109,118,130],"with":[79,94,110,131],"is":[83,103],"reduced":[84,104],"from":[85],"33.4%":[86],"21.8%":[88],"compared":[89,107,116],"MMPG.":[96],"On":[97],"other":[99],"hand,":[100],"12.35%":[106],"86.77%":[115],"without":[119],"Moreover,":[123],"ability":[125],"noise":[127],"immunity":[128],"also":[135],"be":[136],"improved.":[137]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}