{"id":"https://openalex.org/W2578471191","doi":"https://doi.org/10.1109/apccas.2016.7803915","title":"Lateral silicon nanowire based standard cell design for higher performance","display_name":"Lateral silicon nanowire based standard cell design for higher performance","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W2578471191","doi":"https://doi.org/10.1109/apccas.2016.7803915","mag":"2578471191"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2016.7803915","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2016.7803915","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030362624","display_name":"Om Prakash","orcid":"https://orcid.org/0000-0003-1219-2700"},"institutions":[{"id":"https://openalex.org/I154851008","display_name":"Indian Institute of Technology Roorkee","ror":"https://ror.org/00582g326","country_code":"IN","type":"education","lineage":["https://openalex.org/I154851008"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Om. Prakash","raw_affiliation_strings":["E&CE Dept., Indian Institute of Technology, Roorkee, Uttarakhand, India"],"affiliations":[{"raw_affiliation_string":"E&CE Dept., Indian Institute of Technology, Roorkee, Uttarakhand, India","institution_ids":["https://openalex.org/I154851008"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102792137","display_name":"Mohit Sharma","orcid":"https://orcid.org/0000-0002-5680-9111"},"institutions":[{"id":"https://openalex.org/I154851008","display_name":"Indian Institute of Technology Roorkee","ror":"https://ror.org/00582g326","country_code":"IN","type":"education","lineage":["https://openalex.org/I154851008"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"M. Sharma","raw_affiliation_strings":["E&CE Dept., Indian Institute of Technology, Roorkee, Uttarakhand, India"],"affiliations":[{"raw_affiliation_string":"E&CE Dept., Indian Institute of Technology, Roorkee, Uttarakhand, India","institution_ids":["https://openalex.org/I154851008"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031850929","display_name":"Anand Bulusu","orcid":"https://orcid.org/0000-0002-3986-3730"},"institutions":[{"id":"https://openalex.org/I154851008","display_name":"Indian Institute of Technology Roorkee","ror":"https://ror.org/00582g326","country_code":"IN","type":"education","lineage":["https://openalex.org/I154851008"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"A. Bulusu","raw_affiliation_strings":["E&CE Dept., Indian Institute of Technology, Roorkee, Uttarakhand, India"],"affiliations":[{"raw_affiliation_string":"E&CE Dept., Indian Institute of Technology, Roorkee, Uttarakhand, India","institution_ids":["https://openalex.org/I154851008"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067942116","display_name":"Ashok Kumar Saxena","orcid":"https://orcid.org/0000-0003-1251-9320"},"institutions":[{"id":"https://openalex.org/I154851008","display_name":"Indian Institute of Technology Roorkee","ror":"https://ror.org/00582g326","country_code":"IN","type":"education","lineage":["https://openalex.org/I154851008"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"A. K. Saxena","raw_affiliation_strings":["E&CE Dept., Indian Institute of Technology, Roorkee, Uttarakhand, India"],"affiliations":[{"raw_affiliation_string":"E&CE Dept., Indian Institute of Technology, Roorkee, Uttarakhand, India","institution_ids":["https://openalex.org/I154851008"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059645325","display_name":"S. K. Manhas","orcid":"https://orcid.org/0000-0003-3360-9683"},"institutions":[{"id":"https://openalex.org/I154851008","display_name":"Indian Institute of Technology Roorkee","ror":"https://ror.org/00582g326","country_code":"IN","type":"education","lineage":["https://openalex.org/I154851008"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"S. K. Manhas","raw_affiliation_strings":["E&CE Dept., Indian Institute of Technology, Roorkee, Uttarakhand, India"],"affiliations":[{"raw_affiliation_string":"E&CE Dept., Indian Institute of Technology, Roorkee, Uttarakhand, India","institution_ids":["https://openalex.org/I154851008"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5079475933","display_name":"Satish Maheshwaram","orcid":"https://orcid.org/0000-0002-1760-1545"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"S. Maheshwaram","raw_affiliation_strings":["Marri Laxman Reddy Institute of Technology and Management, Hyderabad"],"affiliations":[{"raw_affiliation_string":"Marri Laxman Reddy Institute of Technology and Management, Hyderabad","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5030362624"],"corresponding_institution_ids":["https://openalex.org/I154851008"],"apc_list":null,"apc_paid":null,"fwci":0.1838,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.60953853,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"58","issue":null,"first_page":"135","last_page":"138"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11272","display_name":"Nanowire Synthesis and Applications","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.7182753086090088},{"id":"https://openalex.org/keywords/parasitic-extraction","display_name":"Parasitic extraction","score":0.6990419626235962},{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.6197437047958374},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6187937259674072},{"id":"https://openalex.org/keywords/nanowire","display_name":"Nanowire","score":0.5945310592651367},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.5913146734237671},{"id":"https://openalex.org/keywords/power\u2013delay-product","display_name":"Power\u2013delay product","score":0.5640044212341309},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5450953245162964},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5213804841041565},{"id":"https://openalex.org/keywords/field-effect-transistor","display_name":"Field-effect transistor","score":0.47205668687820435},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.4472200572490692},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.442066490650177},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.43085089325904846},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4290018081665039},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.42621710896492004},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.356703519821167},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.34079664945602417},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.24484476447105408},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18758311867713928},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.13876909017562866},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.10078805685043335},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.08143079280853271}],"concepts":[{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.7182753086090088},{"id":"https://openalex.org/C159818811","wikidata":"https://www.wikidata.org/wiki/Q7135947","display_name":"Parasitic extraction","level":2,"score":0.6990419626235962},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.6197437047958374},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6187937259674072},{"id":"https://openalex.org/C74214498","wikidata":"https://www.wikidata.org/wiki/Q631739","display_name":"Nanowire","level":2,"score":0.5945310592651367},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.5913146734237671},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.5640044212341309},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5450953245162964},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5213804841041565},{"id":"https://openalex.org/C145598152","wikidata":"https://www.wikidata.org/wiki/Q176097","display_name":"Field-effect transistor","level":4,"score":0.47205668687820435},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.4472200572490692},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.442066490650177},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.43085089325904846},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4290018081665039},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.42621710896492004},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.356703519821167},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.34079664945602417},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.24484476447105408},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18758311867713928},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.13876909017562866},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.10078805685043335},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.08143079280853271},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2016.7803915","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2016.7803915","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8299999833106995}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1973339006","https://openalex.org/W2026555177","https://openalex.org/W2049508930","https://openalex.org/W2062627774","https://openalex.org/W2067010371","https://openalex.org/W2068766249","https://openalex.org/W2085355957","https://openalex.org/W2092333682","https://openalex.org/W2106032203","https://openalex.org/W2131842069","https://openalex.org/W2140121956","https://openalex.org/W2155827627","https://openalex.org/W2542085131","https://openalex.org/W6656928341","https://openalex.org/W6676233847","https://openalex.org/W6728890263"],"related_works":["https://openalex.org/W1905216755","https://openalex.org/W2204879205","https://openalex.org/W1998175862","https://openalex.org/W2059812140","https://openalex.org/W2056291972","https://openalex.org/W4256681489","https://openalex.org/W2101848280","https://openalex.org/W2541933328","https://openalex.org/W2578471191","https://openalex.org/W2154289244"],"abstract_inverted_index":{"At":[0],"deep":[1],"nano-scale":[2],"nodes":[3],"Silicon":[4],"Nanowire":[5],"field":[6],"effect":[7,64],"transistor":[8],"(SiNW":[9],"FET)":[10],"imparts":[11],"best":[12],"performance.":[13],"However,":[14],"analysis":[15],"of":[16,132],"SiNW":[17,40],"FET":[18,41],"based":[19,111,121,145],"circuit":[20],"design":[21,31],"is":[22,81],"lacking":[23],"in":[24,43,130],"existing":[25],"literature.":[26],"In":[27],"this":[28],"study,":[29],"we":[30,49,103],"a":[32,51],"standard":[33,91,106,112,122],"cell":[34,92,107],"library":[35,93],"for":[36,75],"advanced":[37],"10nm":[38],"lateral":[39],"technology":[42],"super":[44],"threshold":[45],"regime.":[46],"For":[47],"this,":[48],"create":[50],"Verilog-A":[52,57],"compact":[53,56],"model.":[54],"Our":[55],"model":[58,80],"includes":[59],"all":[60],"the":[61,68,105,117],"short":[62,76],"channel":[63,77],"as":[65,67],"well":[66,82],"geometrical":[69],"dependent":[70],"parasitics,":[71],"which":[72],"are":[73],"crucial":[74],"devices.":[78],"The":[79,90],"calibrated":[83],"with":[84],"TCAD":[85],"and":[86,98,127,137],"reported":[87],"fabricated":[88],"data.":[89],"developed":[94],"comprise":[95],"INVERTER,":[96],"NAND,":[97],"NOR":[99],"gate":[100],"cells.":[101],"Finally,":[102],"compared":[104,142],"performance":[108,129],"to":[109,143],"FinFET":[110,144],"cell.":[113],"We":[114],"found":[115],"that":[116],"Si":[118],"NW":[119],"CMOS":[120],"cells":[123],"have":[124],"~3-4X,":[125],"~2-3X,":[126],"3X":[128],"terms":[131],"power":[133,138],"dissipation,":[134],"energy-delay":[135],"product":[136,140],"delay":[139],"respectively":[141],"designs.":[146]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}