{"id":"https://openalex.org/W2573055209","doi":"https://doi.org/10.1109/apccas.2016.7803891","title":"Embedded hybrid LDO topologies for digital load circuits","display_name":"Embedded hybrid LDO topologies for digital load circuits","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W2573055209","doi":"https://doi.org/10.1109/apccas.2016.7803891","mag":"2573055209"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2016.7803891","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2016.7803891","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071566785","display_name":"Saad Bin Nasir","orcid":"https://orcid.org/0000-0003-1488-0021"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Saad Bin Nasir","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091408102","display_name":"Arijit Raychowdhury","orcid":"https://orcid.org/0000-0001-8391-0576"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Arijit Raychowdhury","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5071566785"],"corresponding_institution_ids":["https://openalex.org/I130701444"],"apc_list":null,"apc_paid":null,"fwci":0.1709,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.59262715,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"43","last_page":"46"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/low-dropout-regulator","display_name":"Low-dropout regulator","score":0.6785587072372437},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.5536624789237976},{"id":"https://openalex.org/keywords/voltage-regulator","display_name":"Voltage regulator","score":0.5422815084457397},{"id":"https://openalex.org/keywords/dropout-voltage","display_name":"Dropout voltage","score":0.489909827709198},{"id":"https://openalex.org/keywords/load-regulation","display_name":"Load regulation","score":0.4728301465511322},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.45883601903915405},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.43225765228271484},{"id":"https://openalex.org/keywords/limit-cycle","display_name":"Limit cycle","score":0.4300975799560547},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4237730801105499},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4201383590698242},{"id":"https://openalex.org/keywords/digital-control","display_name":"Digital control","score":0.4137935936450958},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.4116875231266022},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.34642988443374634},{"id":"https://openalex.org/keywords/limit","display_name":"Limit (mathematics)","score":0.3291410803794861},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.32183289527893066},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14885419607162476},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08325120806694031}],"concepts":[{"id":"https://openalex.org/C140501009","wikidata":"https://www.wikidata.org/wiki/Q6692746","display_name":"Low-dropout regulator","level":5,"score":0.6785587072372437},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.5536624789237976},{"id":"https://openalex.org/C110706871","wikidata":"https://www.wikidata.org/wiki/Q851210","display_name":"Voltage regulator","level":3,"score":0.5422815084457397},{"id":"https://openalex.org/C15032970","wikidata":"https://www.wikidata.org/wiki/Q851210","display_name":"Dropout voltage","level":4,"score":0.489909827709198},{"id":"https://openalex.org/C2776098794","wikidata":"https://www.wikidata.org/wiki/Q6663315","display_name":"Load regulation","level":3,"score":0.4728301465511322},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.45883601903915405},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.43225765228271484},{"id":"https://openalex.org/C93357160","wikidata":"https://www.wikidata.org/wiki/Q1545916","display_name":"Limit cycle","level":3,"score":0.4300975799560547},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4237730801105499},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4201383590698242},{"id":"https://openalex.org/C158411068","wikidata":"https://www.wikidata.org/wiki/Q2720568","display_name":"Digital control","level":2,"score":0.4137935936450958},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.4116875231266022},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.34642988443374634},{"id":"https://openalex.org/C151201525","wikidata":"https://www.wikidata.org/wiki/Q177239","display_name":"Limit (mathematics)","level":2,"score":0.3291410803794861},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.32183289527893066},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14885419607162476},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08325120806694031},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2016.7803891","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2016.7803891","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8799999952316284,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1593782789","https://openalex.org/W1992459337","https://openalex.org/W2057529353","https://openalex.org/W2086284897","https://openalex.org/W2290232850","https://openalex.org/W2291648313","https://openalex.org/W2294756903","https://openalex.org/W2319748949","https://openalex.org/W2343518286","https://openalex.org/W2460563734"],"related_works":["https://openalex.org/W1982997428","https://openalex.org/W4282007662","https://openalex.org/W2737475872","https://openalex.org/W4366165321","https://openalex.org/W1849967185","https://openalex.org/W3081147268","https://openalex.org/W3022411814","https://openalex.org/W2024816799","https://openalex.org/W2086789270","https://openalex.org/W1946066592"],"abstract_inverted_index":{"Digital":[0],"low":[1,37],"dropout":[2,38],"voltage":[3,19,39],"regulators":[4],"provide":[5],"digital":[6,60,118],"process":[7,47],"synthesizability,":[8],"fast":[9],"transient":[10],"response":[11],"and":[12,107],"performance":[13],"adaptation":[14],"but":[15,103],"lack":[16,25],"steady":[17,27,79],"state":[18,28,80],"regulation":[20],"performance.":[21,81],"To":[22],"overcome":[23],"this":[24],"of":[26,58,67,92,99,117],"accuracy":[29],"due":[30],"to":[31,76],"limit":[32,100],"cycle":[33,101],"oscillations,":[34],"a":[35,59,72,87],"hybrid":[36],"regulator":[40,61,70],"topology":[41],"designed":[42],"in":[43,71],"130":[44],"nm":[45],"CMOS":[46],"is":[48],"presented.":[49],"In":[50],"the":[51,54,93],"proposed":[52],"topology,":[53],"operational":[55,115],"discrete":[56],"dynamics":[57,66],"are":[62],"augmented":[63],"with":[64],"continuous":[65],"an":[68],"analog":[69,94],"parallel":[73],"controller":[74,105],"configuration":[75],"achieve":[77],"better":[78],"It":[82],"has":[83],"been":[84],"shown":[85],"that":[86],"higher":[88],"gain":[89],"bandwidth":[90],"product":[91],"LDO":[95],"achieves":[96],"greater":[97],"reduction":[98],"oscillations":[102],"uneven":[104],"strengths":[106],"power":[108],"consumption":[109],"limits":[110],"its":[111],"use":[112],"for":[113],"wide":[114],"range":[116],"load":[119],"circuits.":[120]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}