{"id":"https://openalex.org/W1984142769","doi":"https://doi.org/10.1109/apccas.2014.7032834","title":"Conflict-free FFT circuit using loop architecture by 5-bank memory system","display_name":"Conflict-free FFT circuit using loop architecture by 5-bank memory system","publication_year":2014,"publication_date":"2014-11-01","ids":{"openalex":"https://openalex.org/W1984142769","doi":"https://doi.org/10.1109/apccas.2014.7032834","mag":"1984142769"},"language":"en","primary_location":{"id":"doi:10.1109/apccas.2014.7032834","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2014.7032834","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054328673","display_name":"Takashi Nishitsuji","orcid":"https://orcid.org/0000-0001-8396-5163"},"institutions":[{"id":"https://openalex.org/I159385669","display_name":"Chiba University","ror":"https://ror.org/01hjzeq58","country_code":"JP","type":"education","lineage":["https://openalex.org/I159385669"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Takashi Nishitsuji","raw_affiliation_strings":["Graduate School of Engineering, Chiba University, Chiba, Japan","Graduate School of Engineering, Chiba University, 1-33 Yayoi-cho,#R#Inage-ku, Chiba 263-8522, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Engineering, Chiba University, Chiba, Japan","institution_ids":["https://openalex.org/I159385669"]},{"raw_affiliation_string":"Graduate School of Engineering, Chiba University, 1-33 Yayoi-cho,#R#Inage-ku, Chiba 263-8522, Japan","institution_ids":["https://openalex.org/I159385669"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031873427","display_name":"Takashi Kakue","orcid":"https://orcid.org/0000-0002-7607-0000"},"institutions":[{"id":"https://openalex.org/I159385669","display_name":"Chiba University","ror":"https://ror.org/01hjzeq58","country_code":"JP","type":"education","lineage":["https://openalex.org/I159385669"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Takashi Kakue","raw_affiliation_strings":["Graduate School of Engineering, Chiba University, Chiba, Japan","Graduate School of Engineering, Chiba University, 1-33 Yayoi-cho,#R#Inage-ku, Chiba 263-8522, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Engineering, Chiba University, Chiba, Japan","institution_ids":["https://openalex.org/I159385669"]},{"raw_affiliation_string":"Graduate School of Engineering, Chiba University, 1-33 Yayoi-cho,#R#Inage-ku, Chiba 263-8522, Japan","institution_ids":["https://openalex.org/I159385669"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043329297","display_name":"Tomoyoshi Shimobaba","orcid":"https://orcid.org/0000-0003-1638-7695"},"institutions":[{"id":"https://openalex.org/I159385669","display_name":"Chiba University","ror":"https://ror.org/01hjzeq58","country_code":"JP","type":"education","lineage":["https://openalex.org/I159385669"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Tomoyoshi Shimobaba","raw_affiliation_strings":["Graduate School of Engineering, Chiba University, Chiba, Japan","Graduate School of Engineering, Chiba University, 1-33 Yayoi-cho,#R#Inage-ku, Chiba 263-8522, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Engineering, Chiba University, Chiba, Japan","institution_ids":["https://openalex.org/I159385669"]},{"raw_affiliation_string":"Graduate School of Engineering, Chiba University, 1-33 Yayoi-cho,#R#Inage-ku, Chiba 263-8522, Japan","institution_ids":["https://openalex.org/I159385669"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035089723","display_name":"Tomoyoshi Ito","orcid":"https://orcid.org/0000-0002-6933-0986"},"institutions":[{"id":"https://openalex.org/I159385669","display_name":"Chiba University","ror":"https://ror.org/01hjzeq58","country_code":"JP","type":"education","lineage":["https://openalex.org/I159385669"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Tomoyoshi Ito","raw_affiliation_strings":["Graduate School of Engineering, Chiba University, Chiba, Japan","Graduate School of Engineering, Chiba University, 1-33 Yayoi-cho,#R#Inage-ku, Chiba 263-8522, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Engineering, Chiba University, Chiba, Japan","institution_ids":["https://openalex.org/I159385669"]},{"raw_affiliation_string":"Graduate School of Engineering, Chiba University, 1-33 Yayoi-cho,#R#Inage-ku, Chiba 263-8522, Japan","institution_ids":["https://openalex.org/I159385669"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.06313146,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"523","last_page":"526"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11105","display_name":"Advanced Image Processing Techniques","score":0.9894999861717224,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10688","display_name":"Image and Signal Denoising Methods","score":0.9866999983787537,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/fast-fourier-transform","display_name":"Fast Fourier transform","score":0.8590918183326721},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7240825295448303},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5710371732711792},{"id":"https://openalex.org/keywords/usb","display_name":"USB","score":0.5149484276771545},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.45227792859077454},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.4394259452819824},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4146578907966614},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.16920587420463562},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07860153913497925}],"concepts":[{"id":"https://openalex.org/C75172450","wikidata":"https://www.wikidata.org/wiki/Q623950","display_name":"Fast Fourier transform","level":2,"score":0.8590918183326721},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7240825295448303},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5710371732711792},{"id":"https://openalex.org/C507366226","wikidata":"https://www.wikidata.org/wiki/Q42378","display_name":"USB","level":3,"score":0.5149484276771545},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.45227792859077454},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.4394259452819824},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4146578907966614},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.16920587420463562},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07860153913497925},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apccas.2014.7032834","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apccas.2014.7032834","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2073086065","https://openalex.org/W2144412928"],"related_works":["https://openalex.org/W2362414640","https://openalex.org/W2365301592","https://openalex.org/W2393343175","https://openalex.org/W2389335423","https://openalex.org/W2352432749","https://openalex.org/W2382791190","https://openalex.org/W2376287178","https://openalex.org/W2370750287","https://openalex.org/W2392886890","https://openalex.org/W2359368668"],"abstract_inverted_index":{"We":[0],"developed":[1,36,83],"\"":[2,5,37],"Loop":[3],"architecture":[4],"which":[6],"can":[7],"perform":[8,20,49],"different":[9],"length":[10],"FFT":[11,21,26,51,62],"without":[12],"changing":[13],"fundamental":[14],"circuit":[15,67,77],"composition.":[16],"In":[17,72],"order":[18,47],"to":[19,48,58,78],"effectively,":[22],"we":[23,35,56,74],"adopted":[24],"Mixed-radix":[25,50],"algorithm":[27],"with":[28,65],"radix-2":[29],"and":[30,42,69,82],"radix-4":[31],"butterfly":[32,39],"calculation.":[33],"Furthermore,":[34],"Pipelined":[38],"calculation":[40],"system\"":[41],"\"5-bank":[43],"memory":[44],"architecture\"":[45],"in":[46],"effectively.":[52],"As":[53],"a":[54],"result,":[55],"succeeded":[57],"develop":[59],"the":[60],"versatile":[61],"processing":[63],"system":[64,86],"small":[66],"area":[68],"low":[70],"latency.":[71],"addition,":[73],"implemented":[75],"our":[76],"Spartan-6":[79],"FPGA":[80],"board":[81],"sound":[84],"analysis":[85],"via":[87],"USB.":[88]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
